Lines Matching refs:parent
219 return clk_get_rate(clk->parent); in jz_clk_pll_get_rate()
225 return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; in jz_clk_pll_get_rate()
234 return jz_clk_pll_get_rate(clk->parent); in jz_clk_pll_half_get_rate()
235 return jz_clk_pll_get_rate(clk->parent) >> 1; in jz_clk_pll_half_get_rate()
242 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); in jz_clk_main_round_rate()
269 return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; in jz_clk_main_get_rate()
277 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); in jz_clk_main_set_rate()
314 .parent = &jz_clk_ext.clk,
324 .parent = &jz_clk_pll,
337 .parent = &jz_clk_pll,
346 .parent = &jz_clk_pll,
355 .parent = &jz_clk_pll,
365 .parent = &jz_clk_pll,
379 .parent = &jz_clk_memory.clk,
383 static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent) in jz_clk_spi_set_parent() argument
385 if (parent == &jz_clk_pll) in jz_clk_spi_set_parent()
387 else if (parent == &jz_clk_ext.clk) in jz_clk_spi_set_parent()
392 clk->parent = parent; in jz_clk_spi_set_parent()
397 static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent) in jz_clk_i2s_set_parent() argument
399 if (parent == &jz_clk_pll_half) in jz_clk_i2s_set_parent()
401 else if (parent == &jz_clk_ext.clk) in jz_clk_i2s_set_parent()
406 clk->parent = parent; in jz_clk_i2s_set_parent()
433 static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent) in jz_clk_udc_set_parent() argument
435 if (parent == &jz_clk_pll_half) in jz_clk_udc_set_parent()
437 else if (parent == &jz_clk_ext.clk) in jz_clk_udc_set_parent()
442 clk->parent = parent; in jz_clk_udc_set_parent()
451 if (clk->parent == &jz_clk_ext.clk) in jz_clk_udc_set_rate()
454 div = clk_get_rate(clk->parent) / rate - 1; in jz_clk_udc_set_rate()
470 if (clk->parent == &jz_clk_ext.clk) in jz_clk_udc_get_rate()
471 return clk_get_rate(clk->parent); in jz_clk_udc_get_rate()
477 return clk_get_rate(clk->parent) / div; in jz_clk_udc_get_rate()
485 if (clk->parent == &jz_clk_ext.clk) in jz_clk_divided_get_rate()
486 return clk_get_rate(clk->parent); in jz_clk_divided_get_rate()
490 return clk_get_rate(clk->parent) / div; in jz_clk_divided_get_rate()
498 if (clk->parent == &jz_clk_ext.clk) in jz_clk_divided_set_rate()
501 div = clk_get_rate(clk->parent) / rate - 1; in jz_clk_divided_set_rate()
516 unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent); in jz_clk_ldclk_round_rate()
537 div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; in jz_clk_ldclk_set_rate()
556 return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); in jz_clk_ldclk_get_rate()
571 .parent = &jz_clk_pll_half,
605 .parent = &jz_clk_ext.clk,
615 .parent = &jz_clk_ext.clk,
625 .parent = &jz_clk_pll_half,
635 .parent = &jz_clk_pll_half,
645 .parent = &jz_clk_pll_half,
672 .parent = &jz_clk_ext.clk,
677 .parent = &jz_clk_ext.clk,
683 .parent = &jz_clk_ext.clk,
689 .parent = &jz_clk_high_speed_peripheral.clk,
695 .parent = &jz_clk_high_speed_peripheral.clk,
701 .parent = &jz_clk_ext.clk,
707 .parent = &jz_clk_ext.clk,
713 .parent = &jz_clk_ext.clk,
756 if (clk->parent) in clk_get_rate()
757 return clk_get_rate(clk->parent); in clk_get_rate()
780 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
791 ret = clk->ops->set_parent(clk, parent); in clk_set_parent()
908 jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; in jz4740_clock_init()
913 jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; in jz4740_clock_init()
916 jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half; in jz4740_clock_init()