Lines Matching refs:JZ_REG_CLOCK_CTRL
30 #define JZ_REG_CLOCK_CTRL 0x00 macro
192 jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); in jz_clk_ko_enable()
198 jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); in jz_clk_ko_disable()
204 return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE); in jz_clk_ko_is_enabled()
232 reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz_clk_pll_half_get_rate()
261 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz_clk_main_get_rate()
287 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset, in jz_clk_main_set_rate()
400 jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); in jz_clk_i2s_set_parent()
402 jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); in jz_clk_i2s_set_parent()
436 jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); in jz_clk_udc_set_parent()
438 jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); in jz_clk_udc_set_parent()
461 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET, in jz_clk_udc_set_rate()
473 div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK); in jz_clk_udc_get_rate()
543 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET, in jz_clk_ldclk_set_rate()
553 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK; in jz_clk_ldclk_get_rate()
910 val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz4740_clock_init()