Lines Matching refs:CKSEG1ADDR
38 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
44 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
45 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
46 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
47 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
48 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
49 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
50 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
51 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
52 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
53 #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
54 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
63 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
64 #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
65 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
66 #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
67 #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
68 #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
69 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
70 #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
71 #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
72 #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
73 #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
78 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
79 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
80 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
81 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
82 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
83 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
84 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
85 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
86 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
87 #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
88 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
97 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
98 #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
99 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
100 #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
101 #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
102 #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
103 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
104 #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
105 #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
106 #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
107 #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
110 #define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
120 #define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
121 #define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
122 #define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
123 #define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
124 #define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
125 #define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
126 #define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
127 #define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
128 #define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
129 #define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
130 #define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
131 #define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
132 #define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
133 #define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
134 #define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
135 #define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
140 #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
141 #define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
142 #define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
147 #define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
189 #define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
192 #define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
207 #define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)