Lines Matching refs:MIPS_CM_GCB_OFS
79 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ macro
125 BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00)
126 BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
127 BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
128 BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
129 BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
130 BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
131 BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
132 BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58)
133 BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70)
134 BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80)
135 BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88)
136 BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90)
137 BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98)
138 BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0)
139 BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8)
140 BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0)
141 BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8)
142 BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
143 BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
144 BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
145 BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)