Lines Matching refs:cpu_data
21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
24 #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
27 #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
30 #define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
33 #define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
36 #define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
39 #define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
42 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
55 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
58 #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
63 #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
66 #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
79 #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
82 #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
85 #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
88 #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
91 #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
94 #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
97 #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
100 #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
103 #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
106 #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
109 #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
115 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
118 #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
121 #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
124 #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
129 # define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
131 # define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
137 # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
144 #define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA)
147 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
150 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
153 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
156 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
175 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
185 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
188 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
191 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
194 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
197 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
200 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
203 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
206 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
209 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
212 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
301 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
305 #define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
309 #define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
313 #define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
318 # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
321 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
324 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
354 # define cpu_vmbits cpu_data[0].vmbits
360 # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
366 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
372 #define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
376 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz
379 #define cpu_icache_line_size() cpu_data[0].icache.linesz
382 #define cpu_scache_line_size() cpu_data[0].scache.linesz
390 #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
394 #define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
398 # define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
404 # define cpu_has_fre (cpu_data[0].options & MIPS_CPU_FRE)
408 # define cpu_has_cdmm (cpu_data[0].options & MIPS_CPU_CDMM)