Lines Matching refs:clk_ctrl

243 	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;  in ar934x_clocks_init()  local
310 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_clocks_init()
312 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
315 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_clocks_init()
317 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_clocks_init()
322 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
325 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_clocks_init()
327 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_clocks_init()
332 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
335 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_clocks_init()
337 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) in ar934x_clocks_init()
359 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca955x_clocks_init() local
397 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); in qca955x_clocks_init()
399 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & in qca955x_clocks_init()
402 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) in qca955x_clocks_init()
404 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) in qca955x_clocks_init()
409 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & in qca955x_clocks_init()
412 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in qca955x_clocks_init()
414 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) in qca955x_clocks_init()
419 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & in qca955x_clocks_init()
422 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) in qca955x_clocks_init()
424 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) in qca955x_clocks_init()