266 	unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;  in alchemy_clk_setup_sysbus()  local
270 				      pn, 0, 1, v);  in alchemy_clk_setup_sysbus()
295 	unsigned long v;  in alchemy_clk_setup_mem()  local
302 		v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);  in alchemy_clk_setup_mem()
303 		div = (v & (1 << 15)) ? 1 : 2;  in alchemy_clk_setup_mem()
306 		v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);  in alchemy_clk_setup_mem()
307 		div = (v & (1 << 31)) ? 1 : 2;  in alchemy_clk_setup_mem()
336 	unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);  in alchemy_clk_setup_lrclk()  local
341 		v = 4 + ((v >> 11) & 1);  in alchemy_clk_setup_lrclk()
344 		v = ((v >> 13) & 7) + 1;  in alchemy_clk_setup_lrclk()
347 				      pn, 0, 1, v);  in alchemy_clk_setup_lrclk()
480 	unsigned long v, flags;  in alchemy_clk_fgv1_en()  local
483 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_en()
484 	v |= (1 << 1) << c->shift;  in alchemy_clk_fgv1_en()
485 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_en()
494 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);  in alchemy_clk_fgv1_isen()  local
496 	return v & 1;  in alchemy_clk_fgv1_isen()
502 	unsigned long v, flags;  in alchemy_clk_fgv1_dis()  local
505 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_dis()
506 	v &= ~((1 << 1) << c->shift);  in alchemy_clk_fgv1_dis()
507 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_dis()
514 	unsigned long v, flags;  in alchemy_clk_fgv1_setp()  local
517 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_setp()
519 		v |= (1 << c->shift);  in alchemy_clk_fgv1_setp()
521 		v &= ~(1 << c->shift);  in alchemy_clk_fgv1_setp()
522 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_setp()
539 	unsigned long div, v, flags, ret;  in alchemy_clk_fgv1_setr()  local
546 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv1_setr()
547 	v &= ~(0xff << sh);  in alchemy_clk_fgv1_setr()
548 	v |= div << sh;  in alchemy_clk_fgv1_setr()
549 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv1_setr()
559 	unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);  in alchemy_clk_fgv1_recalc()  local
561 	v = ((v & 0xff) + 1) * 2;  in alchemy_clk_fgv1_recalc()
562 	return parent_rate / v;  in alchemy_clk_fgv1_recalc()
589 	unsigned long v = alchemy_rdsys(c->reg);  in __alchemy_clk_fgv2_en()  local
591 	v &= ~(3 << c->shift);  in __alchemy_clk_fgv2_en()
592 	v |= (c->parent & 3) << c->shift;  in __alchemy_clk_fgv2_en()
593 	alchemy_wrsys(v, c->reg);  in __alchemy_clk_fgv2_en()
620 	unsigned long v, flags;  in alchemy_clk_fgv2_dis()  local
623 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_dis()
624 	v &= ~(3 << c->shift);	/* set input mux to "disabled" state */  in alchemy_clk_fgv2_dis()
625 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv2_dis()
647 	unsigned long flags, v;  in alchemy_clk_fgv2_getp()  local
650 	v = c->parent - 1;  in alchemy_clk_fgv2_getp()
652 	return v;  in alchemy_clk_fgv2_getp()
665 	unsigned long div, v, flags, ret;  in alchemy_clk_fgv2_setr()  local
670 	v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */  in alchemy_clk_fgv2_setr()
671 	ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,  in alchemy_clk_fgv2_setr()
672 			       v ? 256 : 512, &div);  in alchemy_clk_fgv2_setr()
675 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_setr()
676 	v &= ~(0xff << sh);  in alchemy_clk_fgv2_setr()
677 	v |= (div & 0xff) << sh;  in alchemy_clk_fgv2_setr()
678 	alchemy_wrsys(v, c->reg);  in alchemy_clk_fgv2_setr()
689 	unsigned long v, t;  in alchemy_clk_fgv2_recalc()  local
691 	v = alchemy_rdsys(c->reg);  in alchemy_clk_fgv2_recalc()
692 	t = parent_rate / (((v >> sh) & 0xff) + 1);  in alchemy_clk_fgv2_recalc()
693 	if ((v & (1 << 30)) == 0)		/* test scale bit */  in alchemy_clk_fgv2_recalc()
749 	unsigned long v;  in alchemy_clk_init_fgens()  local
790 			v = alchemy_rdsys(a->reg);  in alchemy_clk_init_fgens()
791 			a->parent = (v >> a->shift) & 3;  in alchemy_clk_init_fgens()
816 	unsigned long v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_isen()  local
818 	return (((v >> c->shift) >> 2) & 7) != 0;  in alchemy_clk_csrc_isen()
823 	unsigned long v = alchemy_rdsys(c->reg);  in __alchemy_clk_csrc_en()  local
825 	v &= ~((7 << 2) << c->shift);  in __alchemy_clk_csrc_en()
826 	v |= ((c->parent & 7) << 2) << c->shift;  in __alchemy_clk_csrc_en()
827 	alchemy_wrsys(v, c->reg);  in __alchemy_clk_csrc_en()
847 	unsigned long v, flags;  in alchemy_clk_csrc_dis()  local
850 	v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_dis()
851 	v &= ~((3 << 2) << c->shift);	/* mux to "disabled" state */  in alchemy_clk_csrc_dis()
852 	alchemy_wrsys(v, c->reg);  in alchemy_clk_csrc_dis()
882 	unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;  in alchemy_clk_csrc_recalc()  local
884 	return parent_rate / c->dt[v];  in alchemy_clk_csrc_recalc()
891 	unsigned long d, v, flags;  in alchemy_clk_csrc_setr()  local
911 	v = alchemy_rdsys(c->reg);  in alchemy_clk_csrc_setr()
912 	v &= ~(3 << c->shift);  in alchemy_clk_csrc_setr()
913 	v |= (i & 3) << c->shift;  in alchemy_clk_csrc_setr()
914 	alchemy_wrsys(v, c->reg);  in alchemy_clk_csrc_setr()
959 	unsigned long v;  in alchemy_clk_setup_imux()  local
1013 		v = alchemy_rdsys(a->reg);  in alchemy_clk_setup_imux()
1014 		a->parent = ((v >> a->shift) >> 2) & 7;  in alchemy_clk_setup_imux()