Lines Matching refs:r5
88 lwi r5, r1, 0; \
89 mts rmsr, r5; \
93 lwi r5, r1, PT_R5; \
339 swi r5, r1, PT_R5
348 mfs r5, rmsr;
350 swi r5, r1, 0;
357 andi r5, r4, 0x1000; /* Check ESR[DS] */
358 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
365 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
369 addk r6, r5, r5; /* << 1 */
374 lwi r5, r0, TOPHYS(exception_debug_table)
375 addi r5, r5, 1
376 swi r5, r0, TOPHYS(exception_debug_table)
377 lwi r5, r6, TOPHYS(exception_debug_table)
378 addi r5, r5, 1
379 swi r5, r6, TOPHYS(exception_debug_table)
399 xori r6, r5, 1; /* 00001 = Unaligned Exception */
415 or r5, r1, r0
431 mfs r5, rmsr;
433 ori r5, r5, 2;
434 mts rmsr, r5; /* enable interrupt */
438 mfs r5, rmsr; /* disable interrupt */
440 andi r5, r5, ~2;
441 mts rmsr, r5;
493 lbui r5, r3, 0; /* Exception address in r3 */
496 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
497 lbui r5, r3, 1;
498 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
499 lbui r5, r3, 2;
500 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
501 lbui r5, r3, 3;
502 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
507 lbui r5, r3, 0; /* Exception address in r3 */
510 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
511 lbui r5, r3, 1;
512 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
517 lbui r5, r0, TOPHYS(ex_reg_op);
520 addk r5, r5, r5;
521 addk r5, r5, r5;
522 addk r5, r5, r5;
523 addk r5, r5, r6;
524 bra r5;
528 lbui r5, r0, TOPHYS(ex_reg_op);
531 add r5, r5, r5;
532 add r5, r5, r5;
533 add r5, r5, r5;
534 add r5, r5, r6;
535 bra r5;
565 lwi r5, r1, 0 /* RMSR */
566 mts rmsr, r5
570 lwi r5, r1, PT_R5
603 ori r5, r0, CONFIG_KERNEL_START
604 cmpu r5, r3, r5
605 bgti r5, ex3
632 bsrli r5, r3, PGDIR_SHIFT - 2
633 andi r5, r5, PAGE_SIZE - 4
635 or r4, r4, r5
637 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
638 beqi r5, ex2 /* Bail if no table */
640 tophys(r5,r5)
643 or r5, r5, r6
644 lwi r4, r5, 0 /* Get Linux PTE */
651 swi r4, r5, 0 /* Update Linux page table */
669 mfs r5, rtlbx /* DEBUG: TBD */
733 bsrli r5, r3, PGDIR_SHIFT - 2
734 andi r5, r5, PAGE_SIZE - 4
736 or r4, r4, r5
738 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
739 beqi r5, ex7 /* Bail if no table */
741 tophys(r5,r5)
744 or r5, r5, r6
745 lwi r4, r5, 0 /* Get Linux PTE */
751 swi r4, r5, 0
804 bsrli r5, r3, PGDIR_SHIFT - 2
805 andi r5, r5, PAGE_SIZE - 4
807 or r4, r4, r5
809 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
810 beqi r5, ex10 /* Bail if no table */
812 tophys(r5,r5)
815 or r5, r5, r6
816 lwi r4, r5, 0 /* Get Linux PTE */
822 swi r4, r5, 0
864 lwi r5, r0, TOPHYS(tlb_index)
865 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
868 andi r5, r5, MICROBLAZE_TLB_SIZE - 1
870 cmp r31, r5, r6
872 lwi r5, r0, TOPHYS(tlb_skip)
875 swi r5, r0, TOPHYS(tlb_index)
878 mts rtlbx, r5 /* MS: save current TLB */
926 mts rpid, r5 /* Shadow TLBs are automatically */
956 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
959 sbi r5, r6, 0;
960 load2: lbui r5, r4, 1;
961 sbi r5, r6, 1;
962 load3: lbui r5, r4, 2;
963 sbi r5, r6, 2;
964 load4: lbui r5, r4, 3;
965 sbi r5, r6, 3;
973 sbi r5, r6, 0;
974 load5: lbui r5, r4, 1;
975 sbi r5, r6, 1;
979 addik r5, r8, lw_table_vm;
980 bra r5;
985 addik r5, r8, sw_table_vm;
986 bra r5;
988 addik r5, r0, ex_tmp_data_loc_0;
990 swi r3, r5, 0; /* Get the word - delay slot */
992 lbui r3, r5, 0;
994 lbui r3, r5, 1;
996 lbui r3, r5, 2;
998 lbui r3, r5, 3;
1004 lbui r3, r5, 0;
1006 lbui r3, r5, 1;
1010 lbui r3, r5, 2;
1012 lbui r3, r5, 3;
1024 ori r5, r7, 0 /* setup pointer to pt_regs */