Lines Matching refs:r3
91 lwi r3, r1, PT_R3; \
114 swi r3, r1, 4 * regnum; \
119 or NUM_TO_REG (regnum), r0, r3; \
124 lwi r3, r1, 4 * regnum; \
129 or r3, r0, NUM_TO_REG (regnum); \
135 swi r3, r7, 4 * regnum;
139 or NUM_TO_REG (regnum), r0, r3;
143 lwi r3, r7, 4 * regnum;
147 or r3, r0, NUM_TO_REG (regnum);
337 swi r3, r1, PT_R3
353 mfs r3, rear;
493 lbui r5, r3, 0; /* Exception address in r3 */
497 lbui r5, r3, 1;
499 lbui r5, r3, 2;
501 lbui r5, r3, 3;
507 lbui r5, r3, 0; /* Exception address in r3 */
511 lbui r5, r3, 1;
545 sbi r4, r3, 0;
547 sbi r4, r3, 1;
549 sbi r4, r3, 2;
551 sbi r4, r3, 3;
558 sbi r4, r3, 0;
560 sbi r4, r3, 1;
568 lwi r3, r1, PT_R3
604 cmpu r5, r3, r5
632 bsrli r5, r3, PGDIR_SHIFT - 2
641 bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
667 mts rtlbsx, r3
718 cmpu r4, r3, r6
733 bsrli r5, r3, PGDIR_SHIFT - 2
742 bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
789 cmpu r4, r3, r4
804 bsrli r5, r3, PGDIR_SHIFT - 2
813 bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
887 andi r3, r3, PAGE_MASK
889 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
891 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
893 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
895 mts rtlbhi, r3 /* Load TLB HI */
949 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
951 andi r6, r3, 0x400; /* Extract ESR[S] */
953 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
968 lwi r3, r6, 0;
976 lhui r3, r6, 0; /* Get the destination register value into r3 */
990 swi r3, r5, 0; /* Get the word - delay slot */
992 lbui r3, r5, 0;
993 store1: sbi r3, r4, 0;
994 lbui r3, r5, 1;
995 store2: sbi r3, r4, 1;
996 lbui r3, r5, 2;
997 store3: sbi r3, r4, 2;
998 lbui r3, r5, 3;
1000 store4: sbi r3, r4, 3; /* Delay slot */
1004 lbui r3, r5, 0;
1005 store5: sbi r3, r4, 0;
1006 lbui r3, r5, 1;
1008 store6: sbi r3, r4, 1; /* Delay slot */
1010 lbui r3, r5, 2;
1011 store5: sbi r3, r4, 0;
1012 lbui r3, r5, 3;
1014 store6: sbi r3, r4, 1; /* Delay slot */