Lines Matching refs:x1

51 		#cpus = <0x1>;
69 			xlnx,allow-dcache-wr = <0x1>;
70 			xlnx,allow-icache-wr = <0x1>;
73 			xlnx,d-lmb = <0x1>;
75 			xlnx,d-plb = <0x1>;
78 			xlnx,dcache-always-used = <0x1>;
81 			xlnx,dcache-use-fsl = <0x1>;
82 			xlnx,debug-enabled = <0x1>;
83 			xlnx,div-zero-exception = <0x1>;
85 			xlnx,dynamic-bus-sizing = <0x1>;
86 			xlnx,edge-is-positive = <0x1>;
88 			xlnx,endianness = <0x1>;
89 			xlnx,fpu-exception = <0x1>;
93 			xlnx,i-lmb = <0x1>;
95 			xlnx,i-plb = <0x1>;
96 			xlnx,icache-always-used = <0x1>;
98 			xlnx,icache-use-fsl = <0x1>;
99 			xlnx,ill-opcode-exception = <0x1>;
101 			xlnx,interconnect = <0x1>;
108 			xlnx,number-of-pc-brk = <0x1>;
111 			xlnx,opcode-0x0-illegal = <0x1>;
117 			xlnx,unaligned-exceptions = <0x1>;
118 			xlnx,use-barrel = <0x1>;
119 			xlnx,use-dcache = <0x1>;
120 			xlnx,use-div = <0x1>;
121 			xlnx,use-ext-brk = <0x1>;
122 			xlnx,use-ext-nm-brk = <0x1>;
126 			xlnx,use-icache = <0x1>;
127 			xlnx,use-interrupt = <0x1>;
129 			xlnx,use-msr-instr = <0x1>;
130 			xlnx,use-pcmp-instr = <0x1>;
143 			xlnx,include-datawidth-matching-0 = <0x1>;
148 			xlnx,include-plb-ipif = <0x1>;
149 			xlnx,include-wrbuf = <0x1>;
170 			xlnx,num-banks-mem = <0x1>;
210 			xlnx,xcl0-writexfer = <0x1>;
212 			xlnx,xcl1-writexfer = <0x1>;
214 			xlnx,xcl2-writexfer = <0x1>;
216 			xlnx,xcl3-writexfer = <0x1>;
230 				xlnx,bus2core-clk-ratio = <0x1>;
231 				xlnx,phy-type = <0x1>;
232 				xlnx,phyaddr = <0x1>;
247 			xlnx,gpo-width = <0x1>;
264 			xlnx,interrupt-present = <0x1>;
265 			xlnx,is-bidir = <0x1>;
266 			xlnx,is-bidir-2 = <0x1>;
325 			xlnx,interconnect = <0x1>;
327 			xlnx,mb-dbg-ports = <0x1>;
329 			xlnx,use-uart = <0x1>;
359 			xlnx,gen0-assert = <0x1>;
360 			xlnx,gen1-assert = <0x1>;
362 			xlnx,trig0-assert = <0x1>;
363 			xlnx,trig1-assert = <0x1>;