Lines Matching refs:ushort
22 #define CPM_CR_RST ((ushort)0x8000)
23 #define CPM_CR_OPCODE ((ushort)0x0f00)
24 #define CPM_CR_CHAN ((ushort)0x00f0)
25 #define CPM_CR_FLG ((ushort)0x0001)
28 #define CPM_CR_INIT_TRX ((ushort)0x0000)
29 #define CPM_CR_INIT_RX ((ushort)0x0001)
30 #define CPM_CR_INIT_TX ((ushort)0x0002)
31 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
32 #define CPM_CR_STOP_TX ((ushort)0x0004)
33 #define CPM_CR_GRSTOP_TX ((ushort)0x0005)
34 #define CPM_CR_RESTART_TX ((ushort)0x0006)
35 #define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
36 #define CPM_CR_SET_GADDR ((ushort)0x0008)
37 #define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
38 #define CPM_CR_GCI_ABORT ((ushort)0x000a)
39 #define CPM_CR_RESET_BCS ((ushort)0x000a)
42 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
43 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
44 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
45 #define CPM_CR_CH_TMR ((ushort)0x0005)
46 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
47 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
48 #define CPM_CR_CH_IDMA1 ((ushort)0x0009)
49 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
50 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
51 #define CPM_CR_CH_IDMA2 ((ushort)0x000d)
83 ushort cbd_sc; /* Status and Control */
84 ushort cbd_datlen; /* Data length in buffer */
91 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
92 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
93 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
96 #define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
97 #define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
99 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
100 #define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
102 #define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
103 #define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
105 #define BD_SC_BR ((ushort)0x0020) /* Break received */
106 #define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
108 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
109 #define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
111 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
112 #define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
114 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
115 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
118 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
119 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
120 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
121 #define BD_SC_UN ((ushort)0x0002) /* Underrun */
154 ushort smc_rbase; /* Rx Buffer descriptor base address */
155 ushort smc_tbase; /* Tx Buffer descriptor base address */
158 ushort smc_mrblr; /* Max receive buffer length */
161 ushort smc_rbptr; /* Internal */
162 ushort smc_ibc; /* Internal */
166 ushort smc_tbptr; /* Internal */
167 ushort smc_tbc; /* Internal */
169 ushort smc_maxidl; /* Maximum idle characters */
170 ushort smc_tmpidl; /* Temporary idle counter */
171 ushort smc_brklen; /* Last received break length */
172 ushort smc_brkec; /* rcv'd break condition counter */
173 ushort smc_brkcr; /* xmt break count register */
174 ushort smc_rmask; /* Temporary bit mask */
183 #define SMCMR_REN ((ushort)0x0001)
184 #define SMCMR_TEN ((ushort)0x0002)
185 #define SMCMR_DM ((ushort)0x000c)
186 #define SMCMR_SM_GCI ((ushort)0x0000)
187 #define SMCMR_SM_UART ((ushort)0x0020)
188 #define SMCMR_SM_TRANS ((ushort)0x0030)
189 #define SMCMR_SM_MASK ((ushort)0x0030)
190 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
192 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
194 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
195 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
204 ushort scent_rbase;
205 ushort scent_tbase;
208 ushort scent_mrblr;
211 ushort scent_rbptr;
212 ushort scent_r_cnt;
216 ushort scent_tbptr;
217 ushort scent_t_cnt;
219 ushort scent_max_sl;
220 ushort scent_sl_cnt;
221 ushort scent_character1;
222 ushort scent_character2;
223 ushort scent_character3;
224 ushort scent_character4;
225 ushort scent_character5;
226 ushort scent_character6;
227 ushort scent_character7;
228 ushort scent_character8;
229 ushort scent_rccm;
230 ushort scent_rccr;
341 #define SCC_TODR_TOD ((ushort)0x8000)
351 ushort scc_rbase; /* Rx Buffer descriptor base address */
352 ushort scc_tbase; /* Tx Buffer descriptor base address */
355 ushort scc_mrblr; /* Max receive buffer length */
358 ushort scc_rbptr; /* Internal */
359 ushort scc_ibc; /* Internal */
363 ushort scc_tbptr; /* Internal */
364 ushort scc_tbc; /* Internal */
385 ushort sen_pads; /* Tx short frame pad character */
386 ushort sen_retlim; /* Retry limit threshold */
387 ushort sen_retcnt; /* Retry limit counter */
388 ushort sen_maxflr; /* maximum frame length register */
389 ushort sen_minflr; /* minimum frame length register */
390 ushort sen_maxd1; /* maximum DMA1 length */
391 ushort sen_maxd2; /* maximum DMA2 length */
392 ushort sen_maxd; /* Rx max DMA */
393 ushort sen_dmacnt; /* Rx DMA counter */
394 ushort sen_maxb; /* Max BD byte count */
395 ushort sen_gaddr1; /* Group address filter */
396 ushort sen_gaddr2;
397 ushort sen_gaddr3;
398 ushort sen_gaddr4;
403 ushort sen_tbuf0bcnt; /* Internal */
404 ushort sen_paddrh; /* physical address (MSB) */
405 ushort sen_paddrm;
406 ushort sen_paddrl; /* physical address (LSB) */
407 ushort sen_pper; /* persistence */
408 ushort sen_rfbdptr; /* Rx first BD pointer */
409 ushort sen_tfbdptr; /* Tx first BD pointer */
410 ushort sen_tlbdptr; /* Tx last BD pointer */
415 ushort sen_tbuf1bcnt; /* Internal */
416 ushort sen_txlen; /* Tx Frame length counter */
417 ushort sen_iaddr1; /* Individual address filter */
418 ushort sen_iaddr2;
419 ushort sen_iaddr3;
420 ushort sen_iaddr4;
421 ushort sen_boffcnt; /* Backoff counter */
426 ushort sen_taddrh; /* temp address (MSB) */
427 ushort sen_taddrm;
428 ushort sen_taddrl; /* temp address (LSB) */
468 #define PA_ENET_RXD ((ushort)0x0001)
469 #define PA_ENET_TXD ((ushort)0x0002)
470 #define PA_ENET_TCLK ((ushort)0x0200)
471 #define PA_ENET_RCLK ((ushort)0x0800)
472 #define PC_ENET_TENA ((ushort)0x0001)
473 #define PC_ENET_CLSN ((ushort)0x0010)
474 #define PC_ENET_RENA ((ushort)0x0020)
485 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
486 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
487 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
488 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
489 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
490 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
494 #define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
495 #define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
496 #define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
497 #define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
498 #define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
499 #define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
500 #define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
501 #define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
502 #define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
503 #define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
504 #define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
505 #define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
506 #define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
510 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
511 #define BD_ENET_RX_WRAP ((ushort)0x2000)
512 #define BD_ENET_RX_INTR ((ushort)0x1000)
513 #define BD_ENET_RX_LAST ((ushort)0x0800)
514 #define BD_ENET_RX_FIRST ((ushort)0x0400)
515 #define BD_ENET_RX_MISS ((ushort)0x0100)
516 #define BD_ENET_RX_LG ((ushort)0x0020)
517 #define BD_ENET_RX_NO ((ushort)0x0010)
518 #define BD_ENET_RX_SH ((ushort)0x0008)
519 #define BD_ENET_RX_CR ((ushort)0x0004)
520 #define BD_ENET_RX_OV ((ushort)0x0002)
521 #define BD_ENET_RX_CL ((ushort)0x0001)
522 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
526 #define BD_ENET_TX_READY ((ushort)0x8000)
527 #define BD_ENET_TX_PAD ((ushort)0x4000)
528 #define BD_ENET_TX_WRAP ((ushort)0x2000)
529 #define BD_ENET_TX_INTR ((ushort)0x1000)
530 #define BD_ENET_TX_LAST ((ushort)0x0800)
531 #define BD_ENET_TX_TC ((ushort)0x0400)
532 #define BD_ENET_TX_DEF ((ushort)0x0200)
533 #define BD_ENET_TX_HB ((ushort)0x0100)
534 #define BD_ENET_TX_LC ((ushort)0x0080)
535 #define BD_ENET_TX_RL ((ushort)0x0040)
536 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
537 #define BD_ENET_TX_UN ((ushort)0x0002)
538 #define BD_ENET_TX_CSL ((ushort)0x0001)
539 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
547 ushort scc_maxidl; /* Maximum idle chars */
548 ushort scc_idlc; /* temp idle counter */
549 ushort scc_brkcr; /* Break count register */
550 ushort scc_parec; /* receive parity error counter */
551 ushort scc_frmec; /* receive framing error counter */
552 ushort scc_nosec; /* receive noise counter */
553 ushort scc_brkec; /* receive break condition counter */
554 ushort scc_brkln; /* last received break length */
555 ushort scc_uaddr1; /* UART address character 1 */
556 ushort scc_uaddr2; /* UART address character 2 */
557 ushort scc_rtemp; /* Temp storage */
558 ushort scc_toseq; /* Transmit out of sequence char */
559 ushort scc_char1; /* control character 1 */
560 ushort scc_char2; /* control character 2 */
561 ushort scc_char3; /* control character 3 */
562 ushort scc_char4; /* control character 4 */
563 ushort scc_char5; /* control character 5 */
564 ushort scc_char6; /* control character 6 */
565 ushort scc_char7; /* control character 7 */
566 ushort scc_char8; /* control character 8 */
567 ushort scc_rccm; /* receive control character mask */
568 ushort scc_rccr; /* receive control character register */
569 ushort scc_rlbc; /* receive last break character */
574 #define UART_SCCM_GLR ((ushort)0x1000)
575 #define UART_SCCM_GLT ((ushort)0x0800)
576 #define UART_SCCM_AB ((ushort)0x0200)
577 #define UART_SCCM_IDL ((ushort)0x0100)
578 #define UART_SCCM_GRA ((ushort)0x0080)
579 #define UART_SCCM_BRKE ((ushort)0x0040)
580 #define UART_SCCM_BRKS ((ushort)0x0020)
581 #define UART_SCCM_CCR ((ushort)0x0008)
582 #define UART_SCCM_BSY ((ushort)0x0004)
583 #define UART_SCCM_TX ((ushort)0x0002)
584 #define UART_SCCM_RX ((ushort)0x0001)
588 #define SCU_PMSR_FLC ((ushort)0x8000)
589 #define SCU_PMSR_SL ((ushort)0x4000)
590 #define SCU_PMSR_CL ((ushort)0x3000)
591 #define SCU_PMSR_UM ((ushort)0x0c00)
592 #define SCU_PMSR_FRZ ((ushort)0x0200)
593 #define SCU_PMSR_RZS ((ushort)0x0100)
594 #define SCU_PMSR_SYN ((ushort)0x0080)
595 #define SCU_PMSR_DRT ((ushort)0x0040)
596 #define SCU_PMSR_PEN ((ushort)0x0010)
597 #define SCU_PMSR_RPM ((ushort)0x000c)
598 #define SCU_PMSR_REVP ((ushort)0x0008)
599 #define SCU_PMSR_TPM ((ushort)0x0003)
600 #define SCU_PMSR_TEVP ((ushort)0x0003)
610 #define BD_SCC_TX_LAST ((ushort)0x0800)