Lines Matching refs:r16
226 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
227 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
228 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
233 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
242 mov r16=IA64_TR_KERNEL
252 itr.i itr[r16]=r18
254 itr.d dtr[r16]=r18
261 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
264 mov cr.ipsr=r16
274 SET_AREA_FOR_BOOTING_CPU(r2, r16);
276 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
277 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
314 mov r16=-1
328 shr.u r16=r3,IA64_GRANULE_SHIFT
346 mov IA64_KR(CURRENT_STACK)=r16
401 mov r16=num_hypervisor_hooks
405 cmp.ltu p7,p0=r2,r16 // array size check
460 alloc r16=ar.pfs,1,0,0,0
466 1: mov r16=dbr[r18]
474 st8.nta [in0]=r16,8
483 alloc r16=ar.pfs,1,0,0,0
490 1: ld8.nta r16=[in0],8
494 mov dbr[r18]=r16
934 mov cr.ipsr=r16 // set new PSR
982 mov cr.ipsr=r16 // set new PSR
1075 alloc r16=ar.pfs,1,0,0,0
1101 alloc r16=ar.pfs,1,0,0,0; \
1119 alloc r16=ar.pfs,1,0,0,0;;
1136 movl r16=SAL_PSR_BITS_TO_SET;;
1137 mov cr.ipsr=r16