Lines Matching refs:r2
193 add r2 = TI_FLAGS+IA64_TASK_SIZE,r16
198 ld4 r2 = [r2] // process work pending flags
204 and r2 = TIF_ALLWORK_MASK,r2
209 cmp.ne p6, p0 = 0, r2 // Fallback if work is scheduled
220 ld4 r2 = [r29] // itc_jitter value
229 (p8) cmp.ne p13,p0 = r2,r0 // need itc_jitter compensation, set p13
235 MOV_FROM_ITC(p8, p6, r2, r10) // CPU_TIMER. 36 clocks latency!!!
236 (p9) ld8 r2 = [r30] // MMIO_TIMER. Could also have latency issues..
241 (p13) sub r3 = r25,r2 // Diff needed before comparison (thanks davidm)
244 sub r10 = r2,r24 // current_cycle - last_cycle
249 (p7) cmpxchg8.rel r3 = [r19],r2,ar.ccv
264 getf.sig r2 = f8
268 shr.u r2 = r2,r23 // shift by factor
270 add r8 = r8,r2 // Add xtime.nsecs
276 movl r2 = 1000000000
282 cmp.ge p6,p0 = r8,r2
286 (p6) sub r8 = r8,r2
297 (p14) getf.sig r2 = f8
300 (p14) shr.u r21 = r2, 4
336 add r2=TI_FLAGS+IA64_TASK_SIZE,r16
341 ld4 r2=[r2] // M r2 = thread_info->flags
358 and r2 = TIF_ALLWORK_MASK,r2
360 cmp.ne p8,p0=0,r2
371 and r2 = TIF_ALLWORK_MASK,r2
373 cmp.ne p8,p0=0,r2
472 mov r2=r16 // A get task addr to addl-addressable register
477 addl r22=IA64_RBS_OFFSET,r2 // A compute base of RBS
478 add r3=TI_FLAGS+IA64_TASK_SIZE,r2 // A
505 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // A compute base of memory stack
513 add r16=TI_AC_STAMP+IA64_TASK_SIZE,r2
514 add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r2