Lines Matching refs:r3
252 adds r3=16+64,sp
256 lfetch.fault.excl.nt1 [r3],128
259 lfetch.fault.excl.nt1 [r3],128
262 lfetch.fault.excl [r3]
266 add r3=16,sp
270 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
272 lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
275 lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
286 add r3=SW(F3)+16,sp // r3 = &sw->f3
292 stf.spill [r3]=f3,32
301 stf.spill [r3]=f5,32
313 stf.spill [r3]=f13,32
318 stf.spill [r3]=f15,32
323 stf.spill [r3]=f17,32
326 stf.spill [r3]=f19,32
329 stf.spill [r3]=f21,32
332 stf.spill [r3]=f23,32
335 stf.spill [r3]=f25,32
338 stf.spill [r3]=f27,32
341 stf.spill [r3]=f29,32
344 stf.spill [r3]=f31,SW(PR)-SW(F31)
352 st8 [r3]=r21 // save predicate registers
373 adds r3=SW(AR_UNAT)+16,sp
379 ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
382 ld8 r22=[r3],16 // restore b1
385 ld8 r24=[r3],16 // restore b3
388 ld8 r26=[r3],16 // restore b5
391 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
394 ld8 r30=[r3] // restore rnat
509 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
528 mov r3=NR_syscalls - 1
534 cmp.leu p6,p7=r15,r3
544 adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
550 .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
558 ld8 r3=[r2] // load pt_regs.r8
561 cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
562 adds r3=16,r2 // r3=&pt_regs.r10
734 adds r3=PT(AR_BSPSTORE)+16,r12 // deferred
738 adds r3=PT(AR_BSPSTORE)+16,r12
750 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
756 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
764 ld8 r28=[r3],16 // M0|1 load cr.iip
769 ld8 r25=[r3],16 // M0|1 load ar.unat
776 ld8 r25=[r3],16 // M0|1 load ar.unat
785 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
789 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
793 ld8.fill r1=[r3],16 // M0|1 load r1
801 ld8.fill r13=[r3],16 // M0|1
805 ld8.fill r15=[r3] // M0|1 restore r15
878 adds r3=PT(R16)+16,r12
884 ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
893 ld8 r30=[r3],16 // load ar.csd
897 ld8.fill r8=[r3],16
900 ld8.fill r10=[r3],PT(R17)-PT(R10)
903 ld8.fill r17=[r3],16
906 ld8.fill r19=[r3],16
909 ld8.fill r21=[r3],16
917 ld8.fill r23=[r3],24
921 ld8.fill r26=[r3],16
925 ld8.fill r28=[r3],16
928 ld8.fill r30=[r3],24
931 adds r3=PT(F10)-PT(F6),r3
934 ldf.fill f10=[r3],PT(F8)-PT(F10)
939 ldf.fill f8=[r3],32
945 BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
985 (pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
1006 (pUStk) st8 [r3]=r22 // save time at leave
1010 ld8.fill r3=[r16] // deferred
1015 ld8.fill r3=[r16]
1165 add r3=-8,r3
1168 st8 [r3]=r10
1186 adds r3=PT(R10)+16,r12
1189 ld8 r10=[r3]
1202 ld8 r3=[r2] // load pt_regs.r8
1204 cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
1375 add r3 = 0x20, r3
1381 mov b0 = r3
1388 movl r3 = .here;;
1399 mov b6 = r3
1414 movl r3 = ftrace_trace_function;;
1415 ld8 r3 = [r3];;
1416 ld8 r3 = [r3];;
1417 cmp.eq p7,p0 = r2, r3
1430 mov b6 = r3
1444 mov r3 = b0
1448 mov b7 = r3