Lines Matching refs:r2
114 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
123 (p6) st8 [r2]=in5 // store TLS in r16 for copy_thread()
145 adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
154 (p6) st8 [r2]=in4 // store TLS in r13 (tp)
251 adds r2=16+128,sp
258 lfetch.fault.excl.nt1 [r2],128
261 lfetch.fault.excl [r2]
265 add r2=16+3*128,sp
273 lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
276 lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
282 add r2=SW(F2)+16,sp // r2 = &sw->f2
288 stf.spill [r2]=f2,32
300 stf.spill [r2]=f4,32
312 stf.spill [r2]=f12,32
317 stf.spill [r2]=f14,32
322 stf.spill [r2]=f16,32
325 stf.spill [r2]=f18,32
328 stf.spill [r2]=f20,32
331 stf.spill [r2]=f22,32
334 stf.spill [r2]=f24,32
337 stf.spill [r2]=f26,32
340 stf.spill [r2]=f28,32
343 stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
347 st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
351 st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
354 st8 [r2]=r20 // save ar.bspstore
372 adds r2=SW(AR_BSPSTORE)+16,sp
378 ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
381 ld8 r21=[r2],16 // restore b0
384 ld8 r23=[r2],16 // restore b2
387 ld8 r25=[r2],16 // restore b4
390 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
393 ld8 r28=[r2] // restore pr
508 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
543 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
549 .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
558 ld8 r3=[r2] // load pt_regs.r8
562 adds r3=16,r2 // r3=&pt_regs.r10
624 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
626 ld4 r2=[r2]
629 and r2=_TIF_SYSCALL_TRACEAUDIT,r2
631 cmp.ne p6,p0=r2,r0
639 adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
711 RSM_PSR_I(p0, r2, r18) // disable interrupts
721 RSM_PSR_I(pUStk, r2, r18)
728 adds r2=PT(LOADRS)+16,r12
733 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
737 adds r2=PT(LOADRS)+16,r12
742 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
747 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
755 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
763 ld8 r29=[r2],16 // M0|1 load cr.ipsr
768 ld8 r30=[r2],16 // M0|1 load cr.ifs
775 ld8 r30=[r2],16 // M0|1 load cr.ifs
780 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
784 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
788 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
792 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
804 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
877 adds r2=PT(B6)+16,r12
881 ld8 r28=[r2],8 // load b6
892 ld8 r29=[r2],16 // load b7
896 ld8 r31=[r2],16 // load ar.ssd
899 ld8.fill r9=[r2],16
902 ld8.fill r11=[r2],PT(R18)-PT(R11)
905 ld8.fill r18=[r2],16
908 ld8.fill r20=[r2],16
916 ld8.fill r22=[r2],24
920 ld8.fill r25=[r2],16
924 ld8.fill r27=[r2],16
927 ld8.fill r29=[r2],16
930 ld8.fill r31=[r2],PT(F9)-PT(R31)
933 ldf.fill f9=[r2],PT(F6)-PT(F9)
936 ldf.fill f6=[r2],PT(F7)-PT(F6)
938 ldf.fill f7=[r2],PT(F11)-PT(F7)
944 ldf.fill f11=[r2]
945 BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
997 ld8.fill r2=[r17]
1147 (pLvSys)mov r2=r0
1164 add r2=-8,r2
1167 st8 [r2]=r8
1185 adds r2=PT(R8)+16,r12
1188 ld8 r8=[r2]
1202 ld8 r3=[r2] // load pt_regs.r8
1267 alloc r2=ar.pfs,8,0,1,0
1413 movl r2 = ftrace_stub
1417 cmp.eq p7,p0 = r2, r3
1445 movl r2 = _mcount_ret_helper
1447 mov b6 = r2