23 struct cplb_boundary dcplb_bounds[9] PDT_ATTR;  variable
135 		dcplb_bounds[i_d].eaddr = uncached_end;  in generate_cplb_tables_all()
137 		dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);  in generate_cplb_tables_all()
138 	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;  in generate_cplb_tables_all()
141 		dcplb_bounds[i_d].eaddr = _ramend;  in generate_cplb_tables_all()
142 		dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;  in generate_cplb_tables_all()
146 		dcplb_bounds[i_d].eaddr = physical_mem_end;  in generate_cplb_tables_all()
147 		dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?  in generate_cplb_tables_all()
151 	dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;  in generate_cplb_tables_all()
152 	dcplb_bounds[i_d++].data = 0;  in generate_cplb_tables_all()
154 	dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;  in generate_cplb_tables_all()
155 	dcplb_bounds[i_d++].data = SDRAM_EBIU;  in generate_cplb_tables_all()
157 	dcplb_bounds[i_d].eaddr = BOOT_ROM_START;  in generate_cplb_tables_all()
158 	dcplb_bounds[i_d++].data = 0;  in generate_cplb_tables_all()
160 	dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;  in generate_cplb_tables_all()
161 	dcplb_bounds[i_d++].data = SDRAM_DGENERIC;  in generate_cplb_tables_all()
164 		dcplb_bounds[i_d].eaddr = L2_START;  in generate_cplb_tables_all()
165 		dcplb_bounds[i_d++].data = 0;  in generate_cplb_tables_all()
167 		dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;  in generate_cplb_tables_all()
168 		dcplb_bounds[i_d++].data = L2_DMEMORY;  in generate_cplb_tables_all()
171 	BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));  in generate_cplb_tables_all()