52 #define HWC_x2(level) \  argument
54 	level " - An error occurred due to an invalid access to an System MMR location\n" \
55 	level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
56 	level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
57 #define HWC_x3(level) \  argument
59 #define EXC_0x04(level) \  argument
61 	level " - Maybe you forgot to install a custom exception handler?\n"
62 #define HWC_x12(level) \  argument
64 #define HWC_x18(level) \  argument
66 	level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
67 #define HWC_default(level) \  argument
69 #define EXC_0x03(level) \  argument
71 	level " - Please increase the stack size of the application using elf2flt -s option,\n" \
72 	level "   and/or reduce the stack use of the application.\n"
73 #define EXC_0x10(level) \  argument
75 	level " - When the processor is in single step mode, every instruction\n" \
76 	level "   generates an exception. Primarily used for debugging.\n"
77 #define EXC_0x11(level) \  argument
79 	level " - The processor takes this exception when the trace\n" \
80 	level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
81 #define EXC_0x21(level) \  argument
83 	level " - May be used to emulate instructions that are not defined for\n" \
84 	level "   a particular processor implementation.\n"
85 #define EXC_0x22(level) \  argument
87 	level " - See section for multi-issue rules in the Blackfin\n" \
88 	level "   Processor Instruction Set Reference.\n"
89 #define EXC_0x23(level) \  argument
91 	level " - Attempted read or write to Supervisor resource,\n" \
92 	level "   or illegal data memory access. \n"
93 #define EXC_0x24(level) \  argument
95 	level " - Attempted misaligned data memory or data cache access.\n"
96 #define EXC_0x25(level) \  argument
98 	level " - For example, an exception generated while processing a previous exception.\n"
99 #define EXC_0x26(level) \  argument
101 	level " - Used by the MMU to signal a CPLB miss on a data access.\n"
102 #define EXC_0x27(level) \  argument
104 	level " - More than one CPLB entry matches data fetch address.\n"
105 #define EXC_0x28(level) \  argument
107 	level " - There is a watchpoint match, and one of the EMUSW\n" \
108 	level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
109 #define EXC_0x2A(level) \  argument
111 	level " - Attempted misaligned instruction cache fetch.\n"
112 #define EXC_0x2B(level) \  argument
114 	level " - Illegal instruction fetch access (memory protection violation).\n"
115 #define EXC_0x2C(level) \  argument
117 	level " - CPLB miss on an instruction fetch.\n"
118 #define EXC_0x2D(level) \  argument
120 	level " - More than one CPLB entry matches instruction fetch address.\n"
121 #define EXC_0x2E(level) \  argument
123 	level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
124 	level "   Supervisor resources are registers and instructions that are reserved\n" \
125 	level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
126 	level "   only instructions.\n"