Lines Matching refs:x1
45 lsr x1, x0, x2 // extract cache type bits from clidr
46 and x1, x1, #7 // mask of the bits for current cache only
47 cmp x1, #2 // see what cache we have at this level
52 mrs x1, ccsidr_el1 // read the new ccsidr
54 and x2, x1, #7 // extract the length of the cache lines
57 and x4, x4, x1, lsr #3 // find maximum number on the way size
60 and x7, x7, x1, lsr #13 // extract max number of the index size
132 cmp x4, x1
142 cmp x4, x1
165 add x1, x0, x1
170 cmp x0, x1
192 tst x1, x3 // end cache line aligned?
193 bic x1, x1, x3
195 dc civac, x1 // clean & invalidate D / U line
203 cmp x0, x1
221 cmp x0, x1
238 cmp x0, x1
251 add x1, x1, x0
264 add x1, x1, x0