Lines Matching refs:ldr
155 ldr w4, [x3, #VGIC_V3_CPU_HCR]
156 ldr w5, [x3, #VGIC_V3_CPU_VMCR]
157 ldr w25, [x3, #VGIC_V3_CPU_SRE]
172 ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
174 ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
176 6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
178 5: ldr w17, [x3, #VGIC_V3_CPU_AP1R]
184 ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
186 ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
188 6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
190 5: ldr w17, [x3, #VGIC_V3_CPU_AP0R]
202 ldr x20, [x3, #LR_OFFSET(15)]
203 ldr x19, [x3, #LR_OFFSET(14)]
204 ldr x18, [x3, #LR_OFFSET(13)]
205 ldr x17, [x3, #LR_OFFSET(12)]
206 ldr x16, [x3, #LR_OFFSET(11)]
207 ldr x15, [x3, #LR_OFFSET(10)]
208 ldr x14, [x3, #LR_OFFSET(9)]
209 ldr x13, [x3, #LR_OFFSET(8)]
210 ldr x12, [x3, #LR_OFFSET(7)]
211 ldr x11, [x3, #LR_OFFSET(6)]
212 ldr x10, [x3, #LR_OFFSET(5)]
213 ldr x9, [x3, #LR_OFFSET(4)]
214 ldr x8, [x3, #LR_OFFSET(3)]
215 ldr x7, [x3, #LR_OFFSET(2)]
216 ldr x6, [x3, #LR_OFFSET(1)]
217 ldr x5, [x3, #LR_OFFSET(0)]