Lines Matching refs:x3
47 add x3, x0, #VCPU_VGIC_CPU
67 str w4, [x3, #VGIC_V2_CPU_HCR]
68 str w5, [x3, #VGIC_V2_CPU_VMCR]
69 str w6, [x3, #VGIC_V2_CPU_MISR]
70 CPU_LE( str w7, [x3, #VGIC_V2_CPU_EISR] )
71 CPU_LE( str w8, [x3, #(VGIC_V2_CPU_EISR + 4)] )
72 CPU_LE( str w9, [x3, #VGIC_V2_CPU_ELRSR] )
73 CPU_LE( str w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
74 CPU_BE( str w7, [x3, #(VGIC_V2_CPU_EISR + 4)] )
75 CPU_BE( str w8, [x3, #VGIC_V2_CPU_EISR] )
76 CPU_BE( str w9, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
77 CPU_BE( str w10, [x3, #VGIC_V2_CPU_ELRSR] )
78 str w11, [x3, #VGIC_V2_CPU_APR]
85 ldr w4, [x3, #VGIC_CPU_NR_LR]
86 add x3, x3, #VGIC_V2_CPU_LR
89 str w5, [x3], #4
110 add x3, x0, #VCPU_VGIC_CPU
113 ldr w4, [x3, #VGIC_V2_CPU_HCR]
114 ldr w5, [x3, #VGIC_V2_CPU_VMCR]
115 ldr w6, [x3, #VGIC_V2_CPU_APR]
126 ldr w4, [x3, #VGIC_CPU_NR_LR]
127 add x3, x3, #VGIC_V2_CPU_LR
128 1: ldr w5, [x3], #4