Lines Matching refs:ldr

40 	ldr	x2, [x0, #VCPU_KVM]
42 	ldr	x2, [x2, #KVM_VGIC_VCTRL]
50 	ldr	w4, [x2, #GICH_HCR]
51 	ldr	w5, [x2, #GICH_VMCR]
52 	ldr	w6, [x2, #GICH_MISR]
53 	ldr	w7, [x2, #GICH_EISR0]
54 	ldr	w8, [x2, #GICH_EISR1]
55 	ldr	w9, [x2, #GICH_ELRSR0]
56 	ldr	w10, [x2, #GICH_ELRSR1]
57 	ldr	w11, [x2, #GICH_APR]
85 	ldr	w4, [x3, #VGIC_CPU_NR_LR]
87 1:	ldr	w5, [x2], #4
103 	ldr	x2, [x0, #VCPU_KVM]
105 	ldr	x2, [x2, #KVM_VGIC_VCTRL]
113 	ldr	w4, [x3, #VGIC_V2_CPU_HCR]
114 	ldr	w5, [x3, #VGIC_V2_CPU_VMCR]
115 	ldr	w6, [x3, #VGIC_V2_CPU_APR]
126 	ldr	w4, [x3, #VGIC_CPU_NR_LR]
128 1:	ldr	w5, [x3], #4