Lines Matching refs:CRn
242 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
245 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
248 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
251 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
275 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
278 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
281 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
287 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
290 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
308 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
311 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
314 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
317 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
320 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
323 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
326 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
329 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
333 { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
336 { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
340 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
343 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
346 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
350 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
354 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
357 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
360 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
363 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
366 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
369 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
373 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
376 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
379 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
382 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
385 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
389 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
392 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
396 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
399 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
403 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
407 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1011), Op2(0b101),
410 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
414 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
417 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
421 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
425 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
429 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
432 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
435 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
438 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
441 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
444 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
447 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
450 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
453 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
456 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
459 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
462 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
465 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
469 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
472 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
476 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
479 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
482 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
521 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32, \
524 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32, \
527 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32, \
530 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32, \
534 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32, \
544 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
546 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
550 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
553 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
555 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
558 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
560 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
565 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
567 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
570 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
582 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
586 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
589 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
593 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
596 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
610 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
613 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
615 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
617 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
619 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
621 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
623 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
641 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
643 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
644 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
645 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
646 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
647 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
648 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
649 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
650 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
651 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
652 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
653 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
658 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
659 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
660 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
663 { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
664 { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
665 { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
666 { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
667 { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
668 { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
669 { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
670 { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
671 { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
672 { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
673 { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
674 { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
675 { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
677 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
678 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
679 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
680 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
683 { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
685 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
689 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
690 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi },
691 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
733 if (params->CRn != r->CRn) in find_reg()
844 params.CRn = 0; in kvm_handle_cp_64()
895 params.CRn = (hsr >> 10) & 0xf; in kvm_handle_cp_32()
1006 params.CRn = (esr >> 10) & 0xf; in kvm_handle_sys_reg()
1036 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) in index_to_params()
1116 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1118 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1120 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1122 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1124 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1126 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1128 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1130 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1132 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1134 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1136 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1138 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1140 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1142 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1144 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1146 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1148 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1150 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1152 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1360 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | in sys_reg_to_index()