Lines Matching refs:x2
44 add x3, x2, #CPU_XREG_OFFSET(19)
63 str x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
64 str x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
65 str x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
72 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
73 ldr x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
74 ldr x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
80 add x3, x2, #CPU_XREG_OFFSET(31) // SP_EL0
88 add x3, x2, #CPU_XREG_OFFSET(19)
108 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
115 add x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
127 add x3, x2, #CPU_XREG_OFFSET(4)
140 add x3, x2, #CPU_XREG_OFFSET(0)
153 add x3, x2, #CPU_XREG_OFFSET(0)
173 pop x2, x3
193 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
242 add x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
287 add x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
332 add x3, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
377 add x3, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
423 str x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
430 add x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
479 add x3, x2, #CPU_SYSREG_OFFSET(DBGBCR0_EL1)
523 add x3, x2, #CPU_SYSREG_OFFSET(DBGBVR0_EL1)
567 add x3, x2, #CPU_SYSREG_OFFSET(DBGWCR0_EL1)
611 add x3, x2, #CPU_SYSREG_OFFSET(DBGWVR0_EL1)
655 ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
703 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
711 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
724 add x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
734 add x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
742 add x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
755 add x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
763 ldr x2, [x0, #VCPU_HCR_EL2]
764 msr hcr_el2, x2
765 mov x2, #CPTR_EL2_TTA
766 msr cptr_el2, x2
768 mov x2, #(1 << 15) // Trap CP15 Cr=15
769 msr hstr_el2, x2
771 mrs x2, mdcr_el2
772 and x2, x2, #MDCR_EL2_HPMN_MASK
773 orr x2, x2, #(MDCR_EL2_TPM | MDCR_EL2_TPMCR)
774 orr x2, x2, #(MDCR_EL2_TDRA | MDCR_EL2_TDOSA)
780 orr x2, x2, #MDCR_EL2_TDA
782 msr mdcr_el2, x2
786 mov x2, #HCR_RW
787 msr hcr_el2, x2
791 mrs x2, mdcr_el2
792 and x2, x2, #MDCR_EL2_HPMN_MASK
793 msr mdcr_el2, x2
799 ldr x2, [x1, #KVM_VTTBR]
800 msr vttbr_el2, x2
839 ldr x2, [x0, #VCPU_KVM]
840 kern_hyp_va x2
841 ldr w3, [x2, #KVM_TIMER_ENABLED]
858 mrs x2, cnthctl_el2
859 orr x2, x2, #3
860 msr cnthctl_el2, x2
870 mrs x2, cnthctl_el2
871 orr x2, x2, #1
872 bic x2, x2, #2
873 msr cnthctl_el2, x2
875 ldr x2, [x0, #VCPU_KVM]
876 kern_hyp_va x2
877 ldr w3, [x2, #KVM_TIMER_ENABLED]
880 ldr x3, [x2, #KVM_TIMER_CNTVOFF]
882 ldr x2, [x0, #VCPU_TIMER_CNTV_CVAL]
883 msr cntv_cval_el0, x2
887 and x2, x2, #3
888 msr cntv_ctl_el0, x2
932 ldr x2, [x0, #VCPU_HOST_CONTEXT]
933 kern_hyp_va x2
949 add x2, x0, #VCPU_CONTEXT
970 add x2, x0, #VCPU_CONTEXT
988 ldr x2, [x0, #VCPU_HOST_CONTEXT]
989 kern_hyp_va x2
1012 ldr x2, [x0, #KVM_VTTBR]
1013 msr vttbr_el2, x2
1048 ldr x2, [x0, #KVM_VTTBR]
1049 msr vttbr_el2, x2
1086 ldr x2, [x0, #VCPU_HOST_CONTEXT]
1087 kern_hyp_va x2
1093 ldp x2, x3, [x1]
1094 sub x0, x0, x2
1097 mrs x2, elr_el2
1167 push x2, x3
1170 lsr x2, x1, #ESR_ELx_EC_SHIFT
1172 cmp x2, #ESR_ELx_EC_HVC64
1179 pop x2, x3
1195 mov x1, x2
1196 mov x2, x3
1207 cmp x2, #ESR_ELx_EC_DABT_LOW
1209 ccmp x2, x0, #4, ne
1213 and x2, x1, #ESR_ELx_FSC_TYPE
1214 cmp x2, #FSC_PERM
1234 mrs x2, far_el2
1235 at s1e1r, x2
1248 mrs x2, far_el2
1252 str x2, [x0, #VCPU_FAR_EL2]
1263 3: pop x2, x3
1270 push x2, x3