Lines Matching refs:ldr
72 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
73 ldr x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
74 ldr x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
82 ldr x21, [x3, #16]
167 ldr x18, [x3, #144]
485 ldr x20, [x3, #(15 * 8)]
486 ldr x19, [x3, #(14 * 8)]
487 ldr x18, [x3, #(13 * 8)]
488 ldr x17, [x3, #(12 * 8)]
489 ldr x16, [x3, #(11 * 8)]
490 ldr x15, [x3, #(10 * 8)]
491 ldr x14, [x3, #(9 * 8)]
492 ldr x13, [x3, #(8 * 8)]
493 ldr x12, [x3, #(7 * 8)]
494 ldr x11, [x3, #(6 * 8)]
495 ldr x10, [x3, #(5 * 8)]
496 ldr x9, [x3, #(4 * 8)]
497 ldr x8, [x3, #(3 * 8)]
498 ldr x7, [x3, #(2 * 8)]
499 ldr x6, [x3, #(1 * 8)]
500 ldr x5, [x3, #(0 * 8)]
529 ldr x20, [x3, #(15 * 8)]
530 ldr x19, [x3, #(14 * 8)]
531 ldr x18, [x3, #(13 * 8)]
532 ldr x17, [x3, #(12 * 8)]
533 ldr x16, [x3, #(11 * 8)]
534 ldr x15, [x3, #(10 * 8)]
535 ldr x14, [x3, #(9 * 8)]
536 ldr x13, [x3, #(8 * 8)]
537 ldr x12, [x3, #(7 * 8)]
538 ldr x11, [x3, #(6 * 8)]
539 ldr x10, [x3, #(5 * 8)]
540 ldr x9, [x3, #(4 * 8)]
541 ldr x8, [x3, #(3 * 8)]
542 ldr x7, [x3, #(2 * 8)]
543 ldr x6, [x3, #(1 * 8)]
544 ldr x5, [x3, #(0 * 8)]
573 ldr x20, [x3, #(15 * 8)]
574 ldr x19, [x3, #(14 * 8)]
575 ldr x18, [x3, #(13 * 8)]
576 ldr x17, [x3, #(12 * 8)]
577 ldr x16, [x3, #(11 * 8)]
578 ldr x15, [x3, #(10 * 8)]
579 ldr x14, [x3, #(9 * 8)]
580 ldr x13, [x3, #(8 * 8)]
581 ldr x12, [x3, #(7 * 8)]
582 ldr x11, [x3, #(6 * 8)]
583 ldr x10, [x3, #(5 * 8)]
584 ldr x9, [x3, #(4 * 8)]
585 ldr x8, [x3, #(3 * 8)]
586 ldr x7, [x3, #(2 * 8)]
587 ldr x6, [x3, #(1 * 8)]
588 ldr x5, [x3, #(0 * 8)]
617 ldr x20, [x3, #(15 * 8)]
618 ldr x19, [x3, #(14 * 8)]
619 ldr x18, [x3, #(13 * 8)]
620 ldr x17, [x3, #(12 * 8)]
621 ldr x16, [x3, #(11 * 8)]
622 ldr x15, [x3, #(10 * 8)]
623 ldr x14, [x3, #(9 * 8)]
624 ldr x13, [x3, #(8 * 8)]
625 ldr x12, [x3, #(7 * 8)]
626 ldr x11, [x3, #(6 * 8)]
627 ldr x10, [x3, #(5 * 8)]
628 ldr x9, [x3, #(4 * 8)]
629 ldr x8, [x3, #(3 * 8)]
630 ldr x7, [x3, #(2 * 8)]
631 ldr x6, [x3, #(1 * 8)]
632 ldr x5, [x3, #(0 * 8)]
655 ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
672 ldr \tmp, [x0, #VCPU_DEBUG_FLAGS]
682 ldr x25, [x25, #CPU_SYSREG_OFFSET(MDSCR_EL1)]
744 ldr x6, [x3, #16]
750 ldr x7, [x3, #24]
763 ldr x2, [x0, #VCPU_HCR_EL2]
778 ldr x3, [x0, #VCPU_DEBUG_FLAGS]
797 ldr x1, [x0, #VCPU_KVM]
799 ldr x2, [x1, #KVM_VTTBR]
812 ldr x24, [x24, VGIC_SAVE_FN]
827 ldr x25, [x0, #VCPU_IRQ_LINES]
832 ldr x24, [x24, #VGIC_RESTORE_FN]
839 ldr x2, [x0, #VCPU_KVM]
841 ldr w3, [x2, #KVM_TIMER_ENABLED]
875 ldr x2, [x0, #VCPU_KVM]
877 ldr w3, [x2, #KVM_TIMER_ENABLED]
880 ldr x3, [x2, #KVM_TIMER_CNTVOFF]
882 ldr x2, [x0, #VCPU_TIMER_CNTV_CVAL]
886 ldr w2, [x0, #VCPU_TIMER_CNTV_CTL]
932 ldr x2, [x0, #VCPU_HOST_CONTEXT]
988 ldr x2, [x0, #VCPU_HOST_CONTEXT]
1012 ldr x2, [x0, #KVM_VTTBR]
1048 ldr x2, [x0, #KVM_VTTBR]
1086 ldr x2, [x0, #VCPU_HOST_CONTEXT]
1107 ldr lr, =panic