Lines Matching refs:names
115 clock-output-names = "refclk";
122 clock-names = "pcppll";
124 clock-output-names = "pcppll";
132 clock-names = "socpll";
134 clock-output-names = "socpll";
142 clock-names = "socplldiv2";
145 clock-output-names = "socplldiv2";
152 clock-names = "qmlclk";
154 reg-names = "csr-reg";
155 clock-output-names = "qmlclk";
162 clock-names = "ethclk";
164 reg-names = "div-reg";
168 clock-output-names = "ethclk";
176 reg-names = "csr-reg";
177 clock-output-names = "menetclk";
185 reg-names = "csr-reg";
187 clock-output-names = "sge0clk";
195 reg-names = "csr-reg";
197 clock-output-names = "sge1clk";
205 reg-names = "csr-reg";
207 clock-output-names = "xge0clk";
215 reg-names = "csr-reg";
216 clock-output-names = "sataphy1clk";
229 reg-names = "csr-reg";
230 clock-output-names = "sataphy2clk";
243 reg-names = "csr-reg";
244 clock-output-names = "sataphy3clk";
257 reg-names = "csr-reg";
258 clock-output-names = "sata01clk";
270 reg-names = "csr-reg";
271 clock-output-names = "sata23clk";
283 reg-names = "csr-reg";
284 clock-output-names = "sata45clk";
296 reg-names = "csr-reg";
301 clock-output-names = "rtcclk";
309 reg-names = "csr-reg";
314 clock-output-names = "rngpkaclk";
323 reg-names = "csr-reg";
324 clock-output-names = "pcie0clk";
333 reg-names = "csr-reg";
334 clock-output-names = "pcie1clk";
343 reg-names = "csr-reg";
344 clock-output-names = "pcie2clk";
353 reg-names = "csr-reg";
354 clock-output-names = "pcie3clk";
363 reg-names = "csr-reg";
364 clock-output-names = "pcie4clk";
372 reg-names = "csr-reg";
373 clock-output-names = "dmaclk";
386 reg-names = "csr", "cfg";
409 reg-names = "csr", "cfg";
432 reg-names = "csr", "cfg";
455 reg-names = "csr", "cfg";
478 reg-names = "csr", "cfg";
578 phy-names = "sata-phy";
593 phy-names = "sata-phy";
607 phy-names = "sata-phy";
624 reg-names = "enet_csr", "ring_csr", "ring_cmd";
650 reg-names = "enet_csr", "ring_csr", "ring_cmd";
665 reg-names = "enet_csr", "ring_csr", "ring_cmd";
681 reg-names = "enet_csr", "ring_csr", "ring_cmd";