58 	seq_printf(s, "DMA channel %d requesters list :\n", chan);  in dbg_show_requester_chan()
62 			seq_printf(s, "\tRequester %d (MAPVLD=%d)\n",  in dbg_show_requester_chan()
96 	seq_printf(s, "DMA channel %d descriptors :\n", chan);  in dbg_show_descriptors()
97 	seq_printf(s, "[%03d] First descriptor unknown\n", 0);  in dbg_show_descriptors()
104 		seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",  in dbg_show_descriptors()
106 		seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);  in dbg_show_descriptors()
107 		seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);  in dbg_show_descriptors()
108 		seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);  in dbg_show_descriptors()
109 		seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",  in dbg_show_descriptors()
119 		seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",  in dbg_show_descriptors()
122 		seq_printf(s, "[%03d] Desc at %08lx is %s\n",  in dbg_show_descriptors()
143 	seq_printf(s, "DMA channel %d\n", chan);  in dbg_show_chan_state()
144 	seq_printf(s, "\tPriority : %s\n", str_prio[dma_channels[chan].prio]);  in dbg_show_chan_state()
145 	seq_printf(s, "\tUnaligned transfer bit: %s\n",  in dbg_show_chan_state()
147 	seq_printf(s, "\tDCSR  = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",  in dbg_show_chan_state()
156 	seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",  in dbg_show_chan_state()
162 	seq_printf(s, "\tDSADR = %08x\n", DSADR(chan));  in dbg_show_chan_state()
163 	seq_printf(s, "\tDTADR = %08x\n", DTADR(chan));  in dbg_show_chan_state()
164 	seq_printf(s, "\tDDADR = %08x\n", DDADR(chan));  in dbg_show_chan_state()
173 	seq_printf(s, "\tChannel number: %d\n", num_dma_channels);  in dbg_show_state()