360 	struct irq_chip_type *ct = irq_data_get_chip_type(d);  in gpio_irq_set_type()  local
377 	if (!(ct->type & type))  in gpio_irq_set_type()
504 	struct irq_chip_type *ct = irq_data_get_chip_type(d);  in orion_gpio_unmask_irq()  local
509 	reg_val = irq_reg_readl(gc, ct->regs.mask);  in orion_gpio_unmask_irq()
511 	irq_reg_writel(gc, reg_val, ct->regs.mask);  in orion_gpio_unmask_irq()
518 	struct irq_chip_type *ct = irq_data_get_chip_type(d);  in orion_gpio_mask_irq()  local
523 	reg_val = irq_reg_readl(gc, ct->regs.mask);  in orion_gpio_mask_irq()
525 	irq_reg_writel(gc, reg_val, ct->regs.mask);  in orion_gpio_mask_irq()
537 	struct irq_chip_type *ct;  in orion_gpio_init()  local
594 	ct = gc->chip_types;  in orion_gpio_init()
595 	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;  in orion_gpio_init()
596 	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;  in orion_gpio_init()
597 	ct->chip.irq_mask = orion_gpio_mask_irq;  in orion_gpio_init()
598 	ct->chip.irq_unmask = orion_gpio_unmask_irq;  in orion_gpio_init()
599 	ct->chip.irq_set_type = gpio_irq_set_type;  in orion_gpio_init()
600 	ct->chip.name = ochip->chip.label;  in orion_gpio_init()
602 	ct++;  in orion_gpio_init()
603 	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;  in orion_gpio_init()
604 	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;  in orion_gpio_init()
605 	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;  in orion_gpio_init()
606 	ct->chip.irq_ack = irq_gc_ack_clr_bit;  in orion_gpio_init()
607 	ct->chip.irq_mask = orion_gpio_mask_irq;  in orion_gpio_init()
608 	ct->chip.irq_unmask = orion_gpio_unmask_irq;  in orion_gpio_init()
609 	ct->chip.irq_set_type = gpio_irq_set_type;  in orion_gpio_init()
610 	ct->handler = handle_edge_irq;  in orion_gpio_init()
611 	ct->chip.name = ochip->chip.label;  in orion_gpio_init()