Lines Matching refs:r5
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 stmia r0!, {r4 - r5}
105 mrrc p15, 1, r5, r7, c2 @ TTB 1
114 stmia r0, {r5 - r11}
122 ldmia r0!, {r4 - r5}
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
125 ldmia r0, {r5 - r11}
131 mcrr p15, 1, r5, r7, c2 @ TTB 1
140 ldr r5, =NMRR @ NMRR
142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
184 stmfd sp!, {r4 - r5}
186 mrc p15, 0, r5, c15, c0, 0 @ Power register
187 stmia r0!, {r4 - r5}
188 ldmfd sp!, {r4 - r5}
193 ldmia r0!, {r4 - r5}
198 teq r5, r10 @ Already restored?
199 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
272 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
274 ldmia r12, {r0-r5, lr}
341 stmia r12, {r0-r5, lr} @ v7_invalidate_l1 touches r0-r6
343 ldmia r12, {r0-r5, lr}
350 and r5, r0, #0x00f00000 @ variant
352 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
361 teq r5, #0x00100000 @ only present in r1p*
402 teq r5, #0x00200000 @ only present in r2p*
432 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
433 ldr r5, =PRRR @ PRRR
435 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
444 mov r5, #0
445 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
451 adr r5, v7_crval
452 ldmia r5, {r5, r6}
455 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
459 bic r0, r0, r5 @ clear bits them