Lines Matching refs:c1

33 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
36 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
55 	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
58 	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
111 	mrc	p15, 0, r8, c1, c0, 0	@ Control register
112 	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
113 	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
144 	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
146 	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
147 	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
224 	mrc	p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
226 	mrc	p15, 1, r8, c15, c1, 2	@ save CP15 - Aux Debug Modes Ctrl 2
227 	mrc	p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
236 	mcr	p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
238 	mcr	p15, 1, r8, c15, c1, 2	@ restore CP15 - Aux Debug Modes Ctrl 2
239 	mcr	p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
276 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
281 	mcreq	p15, 0, r0, c1, c0, 1
311 	mrc	p15, 1,	r0, c15, c1, 1
315 	mcr	p15, 1,	r0, c15, c1, 1
318 	mrc	p15, 1,	r0, c15, c1, 2
321 	mcr	p15, 1,	r0, c15, c1, 2
333 	mrc	p15, 1,	r0, c15, c1, 0
335 	mcr	p15, 1,	r0, c15, c1, 0
362 	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
364 	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
368 	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
371 	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
423 	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
425 	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
440 	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
445 	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
458    	mrc	p15, 0, r0, c1, c0, 0		@ read control register