Lines Matching refs:c6
55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
188 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
237 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
280 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
283 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
284 mcr p15, 0, r0, c6, c4, 0
285 mcr p15, 0, r0, c6, c5, 0
286 mcr p15, 0, r0, c6, c6, 0
287 mcr p15, 0, r0, c6, c7, 0
289 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
290 mcr p15, 0, r0, c6, c4, 1
291 mcr p15, 0, r0, c6, c5, 1
292 mcr p15, 0, r0, c6, c6, 1
293 mcr p15, 0, r0, c6, c7, 1
296 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
297 mcr p15, 0, r0, c6, c0, 1
302 mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM
303 mcr p15, 0, r3, c6, c1, 1
308 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
309 mcr p15, 0, r3, c6, c2, 1