Lines Matching refs:cache
17 which has no memory control unit and cache.
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
67 which has no memory control unit and cache.
140 instruction sequences for cache and TLB operations. Curiously,
159 Branch Target Buffer, Unified TLB and cache line size 16.
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
494 # The cache model
543 ARM Architecture Version 4 TLB with writethrough cache.
548 ARM Architecture Version 4 TLB with writeback cache.
553 ARM Architecture Version 4 TLB with writeback cache and invalidate
554 instruction cache entry.
564 Faraday ARM FA526 architecture, unified TLB with writeback cache
565 and invalidate instruction cache entry. Branch target buffer is
582 tag TLB and possibly cache entries.
736 Say Y here to disable the processor instruction cache. Unless
743 Say Y here to disable the processor data cache. Unless
752 Some cores are synthesizable to have various sized cache. For
754 To support such cache operations, it is efficient to know the size
760 bool "Force write through D-cache"
764 Say Y here to use the data cache in writethrough mode. Unless you
768 bool "Round robin I and D cache replacement algorithm"
771 Say Y here to use the predictable round-robin cache replacement
843 bool "Enable read/write for ownership DMA cache maintenance"
848 cache maintenance operations and the dma_{map,unmap}_area()
849 functions may leave stale cache entries on other CPUs. By
851 DMA cache maintenance functions is performed. These LDR/STR
852 instructions change the cache line state to shared or modified
853 so that the cache operation has the desired effect.
856 not perform speculative loads into the D-cache. For such
857 processors, if cache maintenance operations are not broadcast
858 in hardware, other workarounds are needed (e.g. cache
867 The outer cache has a outer_cache_fns.sync function pointer
868 that can be used to drain the write buffer of the outer cache.
871 bool "Enable the Feroceon L2 cache controller"
876 This option enables the Feroceon L2 cache controller.
879 bool "Force Feroceon L2 cache write through"
882 Say Y here to use the Feroceon L2 cache in writethrough mode.
889 or PL310 cache controller, but where its use is optional.
894 Boards or SoCs which always require the cache controller
900 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
912 The PL310 L2 cache controller implements three types of Clean &
924 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
933 bool "PL310 errata: cache sync operation may be faulty"
937 Under some condition the effect of cache sync operation on
941 is to replace the normal offset of cache sync operation (0x730)
943 This has the same effect as the cache sync operation: store buffer
954 on systems with an outer cache, the store buffer is drained
960 bool "Enable the Tauros2 L2 cache controller"
965 This option enables the Tauros2 L2 cache controller (as
969 bool "Enable the L2 cache on XScale3"
974 This option enables the L2 cache on XScale3.
980 Setting ARM L1 cache line size to 64 Bytes.