Lines Matching refs:r5
257 mov32 r5, TEGRA_CLK_RESET_BASE
387 adr r5, tegra_sdram_pad_save
389 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
392 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
403 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
420 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
422 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
424 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
516 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
518 ldr r1, [r5, #0x0] @ restore EMC_CFG
527 addne r5, r5, #0x20
615 str r0, [r5, #CLK_RESET_SCLK_BURST]
620 str r0, [r5, #CLK_RESET_CCLK_BURST]
622 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
623 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
626 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
628 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
641 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
643 str r0, [r5, #CLK_RESET_PLLP_BASE]
644 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
646 str r0, [r5, #CLK_RESET_PLLA_BASE]
647 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
649 str r0, [r5, #CLK_RESET_PLLC_BASE]
650 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
652 str r0, [r5, #CLK_RESET_PLLX_BASE]
656 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
661 str r0, [r5, #CLK_RESET_SCLK_BURST]