Lines Matching refs:r2
213 str r3, [r2]
214 ldr r0, [r2]
350 mov32 r2, TEGRA_PMC_BASE
351 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
353 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
363 mov32 r2, TEGRA_PMC_BASE
364 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
366 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
407 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
464 ldr r2, [r0, #EMC_EMC_STATUS]
465 ands r2, r2, r1
471 ldr r2, [r0, #EMC_FBIO_CFG5]
473 and r2, r2, #3 @ check DRAM_TYPE
474 cmp r2, #2
478 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
479 str r2, [r0, #EMC_ZQ_CAL]
480 ldr r2, [r7]
481 add r2, r2, #10
482 wait_until r2, r7, r3
488 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
489 str r2, [r0, #EMC_ZQ_CAL]
490 ldr r2, [r7]
491 add r2, r2, #10
492 wait_until r2, r7, r3
497 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
498 str r2, [r0, #EMC_MRW]
499 ldr r2, [r7]
500 add r2, r2, #1
501 wait_until r2, r7, r3
507 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
508 str r2, [r0, #EMC_MRW]
509 ldr r2, [r7]
510 add r2, r2, #1
511 wait_until r2, r7, r3
676 cpu_to_csr_reg r2, r1
677 ldr r0, [r6, r2]
680 str r0, [r6, r2]
688 cpu_to_halt_reg r2, r1
689 str r0, [r6, r2]
691 ldr r0, [r6, r2] /* memory barrier */
717 adreq r2, tegra30_sdram_pad_address
720 adreq r2, tegra114_sdram_pad_address
723 adreq r2, tegra124_sdram_pad_address
729 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
762 wait_until r1, r7, r2
783 ldr r2, [r0, #EMC_EMC_STATUS]
784 and r2, r2, r1
785 cmp r2, r1
790 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
791 and r1, r1, r2