Lines Matching refs:r5
360 mov r5, #0
364 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
366 ldr r1, [r4, r5]
369 add r5, r5, #4
370 cmp r6, r5
436 str r0, [r5, #CLK_RESET_SCLK_BURST]
437 str r0, [r5, #CLK_RESET_CCLK_BURST]
439 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
440 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
449 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
451 str r0, [r5, #CLK_RESET_PLLM_BASE]
452 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
454 str r0, [r5, #CLK_RESET_PLLP_BASE]
455 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
457 str r0, [r5, #CLK_RESET_PLLC_BASE]
461 str r0, [r5, #CLK_RESET_SCLK_BURST]
521 mov r5, #0
525 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
528 str r1, [r4, r5] @ save the content of the addr
530 ldr r1, [r3, r5]
533 add r5, r5, #4
534 cmp r6, r5
538 mov32 r5, TEGRA_CLK_RESET_BASE
539 ldr r0, [r5, #CLK_RESET_SCLK_BURST]