Lines Matching refs:r2
101 ldr r2, =__tegra20_cpu1_resettable_status_offset
103 strb r12, [r1, r2]
107 mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
108 str r2, [r3, r1] @ put flow controller in wait event mode
109 ldr r2, [r3, r1]
152 addeq r2, r3, #PMC_SCRATCH38
154 addne r2, r3, #PMC_SCRATCH39
158 str r12, [r2] @ flag[cpu] = 1
176 addeq r2, r3, #PMC_SCRATCH38
177 addne r2, r3, #PMC_SCRATCH39
179 str r12, [r2]
191 ldr r2, =__tegra20_cpu1_resettable_status_offset
193 strb r12, [r1, r2]
205 ldr r2, =__tegra20_cpu1_resettable_status_offset
207 strb r12, [r1, r2]
219 ldr r2, =__tegra20_cpu1_resettable_status_offset
220 ldrb r12, [r1, r2]
358 adr r2, tegra20_sdram_pad_address
364 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
401 ldr r2, [r0, #EMC_EMC_STATUS]
402 ands r2, r2, r1
499 mov r2, #3
500 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
503 ldr r2, [r1, #EMC_EMC_STATUS]
504 tst r2, #4
507 mov r2, #1
508 str r2, [r1, #EMC_SELF_REF]
510 emc_device_mask r2, r1
514 and r3, r3, r2
515 cmp r3, r2
518 adr r2, tegra20_sdram_pad_address
525 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
540 adr r2, tegra20_sclk_save
541 str r0, [r2]