Lines Matching refs:cpu
24 #define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64) argument
25 #define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40) argument
26 #define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04) argument
27 #define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08) argument
35 #define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140) argument
71 static int sun6i_smp_boot_secondary(unsigned int cpu, in sun6i_smp_boot_secondary() argument
87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary()
95 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()
99 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); in sun6i_smp_boot_secondary()
104 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary()
108 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary()
112 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary()