Lines Matching refs:__raw_readl
98 if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) { in pll_recalc()
99 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); in pll_recalc()
104 if (__raw_readl(clk->enable_reg) & (1 << 20)) in pll_recalc()
191 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); in frqcr_kick()
193 if (__raw_readl(FRQCRB) & (1 << 31)) in frqcr_kick()
271 __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); in zclk_set_rate()
280 __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); in zclk_set_rate()
317 if (__raw_readl(FRQCRB) & (1 << 28)) in zclk_recalc()
325 if (__raw_readl(FRQCRB) & (1 << 31)) in kicker_set_rate()
444 value = __raw_readl(clk->mapping->base); in dsiphy_recalc()
471 value = __raw_readl(clk->mapping->base); in dsiphy_disable()
482 value = __raw_readl(clk->mapping->base); in dsiphy_enable()
504 value = __raw_readl(clk->mapping->base); in dsiphy_set_rate()
713 switch ((__raw_readl(CKSCR) >> 28) & 0x03) { in sh73a0_clock_init()