Lines Matching refs:FShft
142 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
148 (((Size) - 1) << FShft (UDCIMP_INMAXP))
342 FShft (UTCR1_BRD))
345 FShft (UTCR2_BRD))
350 FShft (UTCR1_BRD))
353 FShft (UTCR2_BRD))
481 FShft (SDCR3_BRD))
484 FShft (SDCR4_BRD))
489 FShft (SDCR3_BRD))
492 FShft (SDCR4_BRD))
642 ((Div)/32 << FShft (MCCR0_ASD))
646 (((Div) + 31)/32 << FShft (MCCR0_ASD))
655 ((Div)/32 << FShft (MCCR0_TSD))
659 (((Div) + 31)/32 << FShft (MCCR0_TSD))
681 (((Div) - 1) << FShft (MCCR0_ECP))
759 (((Size) - 1) << FShft (SSCR0_DSS))
763 (0 << FShft (SSCR0_FRF))
766 (1 << FShft (SSCR0_FRF))
768 (2 << FShft (SSCR0_FRF))
774 (((Div) - 2)/2 << FShft (SSCR0_SCR))
778 (((Div) - 1)/2 << FShft (SSCR0_SCR))
980 (0x00 << FShft (PPCR_CCF))
982 (0x01 << FShft (PPCR_CCF))
984 (0x02 << FShft (PPCR_CCF))
986 (0x03 << FShft (PPCR_CCF))
988 (0x04 << FShft (PPCR_CCF))
990 (0x05 << FShft (PPCR_CCF))
992 (0x06 << FShft (PPCR_CCF))
994 (0x07 << FShft (PPCR_CCF))
996 (0x08 << FShft (PPCR_CCF))
998 (0x09 << FShft (PPCR_CCF))
1000 (0x0A << FShft (PPCR_CCF))
1002 (0x0B << FShft (PPCR_CCF))
1004 (0x0C << FShft (PPCR_CCF))
1006 (0x0D << FShft (PPCR_CCF))
1008 (0x0E << FShft (PPCR_CCF))
1010 (0x0F << FShft (PPCR_CCF))
1094 (0 << FShft (TUCR_TSEL))
1096 (1 << FShft (TUCR_TSEL))
1098 (2 << FShft (TUCR_TSEL))
1100 (3 << FShft (TUCR_TSEL))
1103 (4 << FShft (TUCR_TSEL))
1106 (5 << FShft (TUCR_TSEL))
1108 (6 << FShft (TUCR_TSEL))
1110 (7 << FShft (TUCR_TSEL))
1415 (((Add) - 9) << FShft (MDCNFG_DRAC))
1420 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1422 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1425 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1427 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1430 ((Tcpu) << FShft (MDCNFG_TDL))
1435 ((Tcpu)/8 << FShft (MDCNFG_DRI))
1489 (0 << FShft (MSC_RT))
1491 (1 << FShft (MSC_RT))
1493 (2 << FShft (MSC_RT))
1495 (3 << FShft (MSC_RT))
1503 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1505 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1508 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1510 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1515 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1517 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1520 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1522 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1526 (((Tcpu)/4) << FShft (MSC_RRR))
1528 ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1555 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1557 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1561 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1563 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1566 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1568 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1667 (0 << FShft (LCD_PBS))
1669 (1 << FShft (LCD_PBS))
1671 (2 << FShft (LCD_PBS))
1722 ((Tcpu)/2 << FShft (LCCR0_PDD))
1747 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
1752 (((Tpix) - 1) << FShft (LCCR1_HSW))
1757 (((Tpix) - 1) << FShft (LCCR1_ELW))
1762 (((Tpix) - 1) << FShft (LCCR1_BLW))
1766 (((Line) - 1) << FShft (LCCR2_LPP))
1771 (((Tln) - 1) << FShft (LCCR2_VSW))
1776 ((Tln) << FShft (LCCR2_EFW))
1781 ((Tln) << FShft (LCCR2_BFW))
1788 (((Div) - 4)/2 << FShft (LCCR3_PCD))
1792 (((Div) - 3)/2 << FShft (LCCR3_PCD))
1798 (((Div) - 2)/2 << FShft (LCCR3_ACB))
1802 (((Div) - 1)/2 << FShft (LCCR3_ACB))
1809 (0 << FShft (LCCR3_API))
1812 ((Trans) << FShft (LCCR3_API))