340 #define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
341                 	(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
343 #define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
344                 	(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
348 #define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
349                 	(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
351 #define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
352                 	(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
479 #define SDCR3_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
480                 	(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
482 #define SDCR4_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
483                 	(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
487 #define SDCR3_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
488                 	(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
490 #define SDCR4_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
491                 	(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
640 #define MCCR0_AudSmpDiv(Div)    	/*  Audio Sampling rate Divisor    */ \  argument
642                 	((Div)/32 << FShft (MCCR0_ASD))
645 #define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \  argument
646                 	(((Div) + 31)/32 << FShft (MCCR0_ASD))
653 #define MCCR0_TcmSmpDiv(Div)    	/*  Telecom Sampling rate Divisor  */ \  argument
655                 	((Div)/32 << FShft (MCCR0_TSD))
658 #define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \  argument
659                 	(((Div) + 31)/32 << FShft (MCCR0_TSD))
680 #define MCCR0_ExtClkDiv(Div)    	/*  External Clock Divisor [1..4]  */ \  argument
681                 	(((Div) - 1) << FShft (MCCR0_ECP))
773 #define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \  argument
774                 	(((Div) - 2)/2 << FShft (SSCR0_SCR))
777 #define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \  argument
778                 	(((Div) - 1)/2 << FShft (SSCR0_SCR))
1787 #define LCCR3_PixClkDiv(Div)    	/*  Pixel Clock Divisor [6..514]   */ \  argument
1788                 	(((Div) - 4)/2 << FShft (LCCR3_PCD))
1791 #define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \  argument
1792                 	(((Div) - 3)/2 << FShft (LCCR3_PCD))
1797 #define LCCR3_ACBsDiv(Div)      	/*  AC Bias clock Divisor [2..512] */ \  argument
1798                 	(((Div) - 2)/2 << FShft (LCCR3_ACB))
1801 #define LCCR3_CeilACBsDiv(Div)  	/*  Ceil. of ACBsDiv [2..512]      */ \  argument
1802                 	(((Div) - 1)/2 << FShft (LCCR3_ACB))