Lines Matching refs:ldr

138 	ldr	r4, [sp, #52]
140 	ldr	r4, [sp, #56]
142 	ldr	r4, [sp, #60]
144 	ldr	r4, [sp, #64]
146 	ldr	r4, [sp, #68]
150 	ldr	r4, [sp, #72]
152 	ldr	r4, [sp, #76]
154 	ldr	r4, [sp, #80]
184 	ldr	r11, omap3_sdrc_dlla_ctrl
185 	ldr	r12, [r11]
192 	ldr	r11, omap3_sdrc_dlla_ctrl
193 	ldr	r12, [r11]
198 	ldr	r11, omap3_sdrc_power	@ read the SDRC_POWER register
199 	ldr	r12, [r11]		@ read the contents of SDRC_POWER
203 	ldr	r12, [r11]		@ posted-write barrier for SDRC
205 	ldr	r11, omap3_cm_iclken1_core	@ read the CM_ICLKEN1_CORE reg
206 	ldr	r12, [r11]
210 	ldr 	r11, omap3_cm_idlest1_core
211 	ldr 	r12, [r11]
217 	ldr 	r11, omap3_cm_clksel1_pll
218 	ldr	r12, [r11]
219 	ldr	r10, core_m2_mask_val	@ modify m2 for core dpll
223 	ldr	r12, [r11]		@ posted-write barrier for CM
230 	ldr 	r11, omap3_cm_iclken1_core
231 	ldr	r12, [r11]
235 	ldr 	r11, omap3_cm_idlest1_core
236 	ldr	r12, [r11]
241 	ldr	r11, omap3_sdrc_power
245 	ldr	r11, omap3_sdrc_dlla_status
246 	ldr	r12, [r11]
252 	ldr	r11, omap3_sdrc_dlla_status
253 	ldr	r12, [r11]
259 	ldr	r12, omap_sdrc_rfr_ctrl_0_val	@ fetch value from SRAM
260 	ldr	r11, omap3_sdrc_rfr_ctrl_0	@ fetch addr from SRAM
263 	ldr	r12, omap_sdrc_actim_ctrl_a_0_val
264 	ldr	r11, omap3_sdrc_actim_ctrl_a_0
266 	ldr	r12, omap_sdrc_actim_ctrl_b_0_val
267 	ldr	r11, omap3_sdrc_actim_ctrl_b_0
269 	ldr	r12, omap_sdrc_mr_0_val
270 	ldr	r11, omap3_sdrc_mr_0
273 	ldr	r12, omap_sdrc_rfr_ctrl_1_val
276 	ldr	r11, omap3_sdrc_rfr_ctrl_1
279 	ldr	r12, omap_sdrc_actim_ctrl_a_1_val
280 	ldr	r11, omap3_sdrc_actim_ctrl_a_1
282 	ldr	r12, omap_sdrc_actim_ctrl_b_1_val
283 	ldr	r11, omap3_sdrc_actim_ctrl_b_1
285 	ldr	r12, omap_sdrc_mr_1_val
286 	ldr	r11, omap3_sdrc_mr_1
290 	ldr	r12, [r11]		@ posted-write barrier for SDRC