95 	u8 i;  in _wakeupgen_clear()  local
97 	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))  in _wakeupgen_clear()
100 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_clear()
102 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_clear()
108 	u8 i;  in _wakeupgen_set()  local
110 	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))  in _wakeupgen_set()
113 	val = wakeupgen_readl(i, cpu);  in _wakeupgen_set()
115 	wakeupgen_writel(val, i, cpu);  in _wakeupgen_set()
149 	u8 i;  in _wakeupgen_save_masks()  local
151 	for (i = 0; i < irq_banks; i++)  in _wakeupgen_save_masks()
152 		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);  in _wakeupgen_save_masks()
157 	u8 i;  in _wakeupgen_restore_masks()  local
159 	for (i = 0; i < irq_banks; i++)  in _wakeupgen_restore_masks()
160 		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);  in _wakeupgen_restore_masks()
165 	u8 i;  in _wakeupgen_set_all()  local
167 	for (i = 0; i < irq_banks; i++)  in _wakeupgen_set_all()
168 		wakeupgen_writel(reg, i, cpu);  in _wakeupgen_set_all()
197 	u32 i, val;  in omap4_irq_save_context()  local
202 	for (i = 0; i < irq_banks; i++) {  in omap4_irq_save_context()
204 		val = wakeupgen_readl(i, 0);  in omap4_irq_save_context()
205 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);  in omap4_irq_save_context()
206 		val = wakeupgen_readl(i, 1);  in omap4_irq_save_context()
207 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);  in omap4_irq_save_context()
216 		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);  in omap4_irq_save_context()
217 		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);  in omap4_irq_save_context()
241 	u32 i, val;  in omap5_irq_save_context()  local
243 	for (i = 0; i < irq_banks; i++) {  in omap5_irq_save_context()
245 		val = wakeupgen_readl(i, 0);  in omap5_irq_save_context()
246 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);  in omap5_irq_save_context()
247 		val = wakeupgen_readl(i, 1);  in omap5_irq_save_context()
248 		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);  in omap5_irq_save_context()
249 		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);  in omap5_irq_save_context()
250 		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);  in omap5_irq_save_context()
428 	int i;  in wakeupgen_domain_alloc()  local
439 	for (i = 0; i < nr_irqs; i++)  in wakeupgen_domain_alloc()
440 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,  in wakeupgen_domain_alloc()
461 	int i;  in wakeupgen_init()  local
504 	for (i = 0; i < irq_banks; i++) {  in wakeupgen_init()
505 		wakeupgen_writel(0, i, CPU0_ID);  in wakeupgen_init()
507 			wakeupgen_writel(0, i, CPU1_ID);  in wakeupgen_init()
516 	for (i = 0; i < max_irqs; i++)  in wakeupgen_init()
517 		irq_target_cpu[i] = boot_cpu;  in wakeupgen_init()