45 	const struct dpll_data *dd;  in _omap3_dpll_write_clken()  local
48 	dd = clk->dpll_data;  in _omap3_dpll_write_clken()
50 	v = omap2_clk_readl(clk, dd->control_reg);  in _omap3_dpll_write_clken()
51 	v &= ~dd->enable_mask;  in _omap3_dpll_write_clken()
52 	v |= clken_bits << __ffs(dd->enable_mask);  in _omap3_dpll_write_clken()
53 	omap2_clk_writel(v, clk, dd->control_reg);  in _omap3_dpll_write_clken()
59 	const struct dpll_data *dd;  in _omap3_wait_dpll_status()  local
64 	dd = clk->dpll_data;  in _omap3_wait_dpll_status()
67 	state <<= __ffs(dd->idlest_mask);  in _omap3_wait_dpll_status()
69 	while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)  in _omap3_wait_dpll_status()
136 	const struct dpll_data *dd;  in _omap3_noncore_dpll_lock()  local
143 	dd = clk->dpll_data;  in _omap3_noncore_dpll_lock()
144 	state <<= __ffs(dd->idlest_mask);  in _omap3_noncore_dpll_lock()
147 	if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)  in _omap3_noncore_dpll_lock()
299 	struct dpll_data *dd = clk->dpll_data;  in omap3_noncore_dpll_program()  local
311 		v = omap2_clk_readl(clk, dd->control_reg);  in omap3_noncore_dpll_program()
312 		v &= ~dd->freqsel_mask;  in omap3_noncore_dpll_program()
313 		v |= freqsel << __ffs(dd->freqsel_mask);  in omap3_noncore_dpll_program()
314 		omap2_clk_writel(v, clk, dd->control_reg);  in omap3_noncore_dpll_program()
318 	v = omap2_clk_readl(clk, dd->mult_div1_reg);  in omap3_noncore_dpll_program()
321 	if (dd->dcc_mask) {  in omap3_noncore_dpll_program()
322 		if (dd->last_rounded_rate >= dd->dcc_rate)  in omap3_noncore_dpll_program()
323 			v |= dd->dcc_mask; /* Enable DCC */  in omap3_noncore_dpll_program()
325 			v &= ~dd->dcc_mask; /* Disable DCC */  in omap3_noncore_dpll_program()
328 	v &= ~(dd->mult_mask | dd->div1_mask);  in omap3_noncore_dpll_program()
329 	v |= dd->last_rounded_m << __ffs(dd->mult_mask);  in omap3_noncore_dpll_program()
330 	v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);  in omap3_noncore_dpll_program()
333 	if (dd->dco_mask) {  in omap3_noncore_dpll_program()
334 		_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);  in omap3_noncore_dpll_program()
335 		v &= ~(dd->dco_mask);  in omap3_noncore_dpll_program()
336 		v |= dco << __ffs(dd->dco_mask);  in omap3_noncore_dpll_program()
338 	if (dd->sddiv_mask) {  in omap3_noncore_dpll_program()
339 		_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,  in omap3_noncore_dpll_program()
340 			      dd->last_rounded_n);  in omap3_noncore_dpll_program()
341 		v &= ~(dd->sddiv_mask);  in omap3_noncore_dpll_program()
342 		v |= sd_div << __ffs(dd->sddiv_mask);  in omap3_noncore_dpll_program()
345 	omap2_clk_writel(v, clk, dd->mult_div1_reg);  in omap3_noncore_dpll_program()
348 	if (dd->m4xen_mask || dd->lpmode_mask) {  in omap3_noncore_dpll_program()
349 		v = omap2_clk_readl(clk, dd->control_reg);  in omap3_noncore_dpll_program()
351 		if (dd->m4xen_mask) {  in omap3_noncore_dpll_program()
352 			if (dd->last_rounded_m4xen)  in omap3_noncore_dpll_program()
353 				v |= dd->m4xen_mask;  in omap3_noncore_dpll_program()
355 				v &= ~dd->m4xen_mask;  in omap3_noncore_dpll_program()
358 		if (dd->lpmode_mask) {  in omap3_noncore_dpll_program()
359 			if (dd->last_rounded_lpmode)  in omap3_noncore_dpll_program()
360 				v |= dd->lpmode_mask;  in omap3_noncore_dpll_program()
362 				v &= ~dd->lpmode_mask;  in omap3_noncore_dpll_program()
365 		omap2_clk_writel(v, clk, dd->control_reg);  in omap3_noncore_dpll_program()
412 	struct dpll_data *dd;  in omap3_noncore_dpll_enable()  local
415 	dd = clk->dpll_data;  in omap3_noncore_dpll_enable()
416 	if (!dd)  in omap3_noncore_dpll_enable()
432 	if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {  in omap3_noncore_dpll_enable()
433 		WARN_ON(parent != __clk_get_hw(dd->clk_bypass));  in omap3_noncore_dpll_enable()
436 		WARN_ON(parent != __clk_get_hw(dd->clk_ref));  in omap3_noncore_dpll_enable()
482 	struct dpll_data *dd;  in omap3_noncore_dpll_determine_rate()  local
487 	dd = clk->dpll_data;  in omap3_noncore_dpll_determine_rate()
488 	if (!dd)  in omap3_noncore_dpll_determine_rate()
491 	if (__clk_get_rate(dd->clk_bypass) == rate &&  in omap3_noncore_dpll_determine_rate()
492 	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {  in omap3_noncore_dpll_determine_rate()
493 		*best_parent_clk = __clk_get_hw(dd->clk_bypass);  in omap3_noncore_dpll_determine_rate()
496 		*best_parent_clk = __clk_get_hw(dd->clk_ref);  in omap3_noncore_dpll_determine_rate()
543 	struct dpll_data *dd;  in omap3_noncore_dpll_set_rate()  local
550 	dd = clk->dpll_data;  in omap3_noncore_dpll_set_rate()
551 	if (!dd)  in omap3_noncore_dpll_set_rate()
555 	    __clk_get_hw(dd->clk_ref))  in omap3_noncore_dpll_set_rate()
558 	if (dd->last_rounded_rate == 0)  in omap3_noncore_dpll_set_rate()
563 		freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);  in omap3_noncore_dpll_set_rate()
623 	const struct dpll_data *dd;  in omap3_dpll_autoidle_read()  local
629 	dd = clk->dpll_data;  in omap3_dpll_autoidle_read()
631 	if (!dd->autoidle_reg)  in omap3_dpll_autoidle_read()
634 	v = omap2_clk_readl(clk, dd->autoidle_reg);  in omap3_dpll_autoidle_read()
635 	v &= dd->autoidle_mask;  in omap3_dpll_autoidle_read()
636 	v >>= __ffs(dd->autoidle_mask);  in omap3_dpll_autoidle_read()
652 	const struct dpll_data *dd;  in omap3_dpll_allow_idle()  local
658 	dd = clk->dpll_data;  in omap3_dpll_allow_idle()
660 	if (!dd->autoidle_reg)  in omap3_dpll_allow_idle()
668 	v = omap2_clk_readl(clk, dd->autoidle_reg);  in omap3_dpll_allow_idle()
669 	v &= ~dd->autoidle_mask;  in omap3_dpll_allow_idle()
670 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);  in omap3_dpll_allow_idle()
671 	omap2_clk_writel(v, clk, dd->autoidle_reg);  in omap3_dpll_allow_idle()
683 	const struct dpll_data *dd;  in omap3_dpll_deny_idle()  local
689 	dd = clk->dpll_data;  in omap3_dpll_deny_idle()
691 	if (!dd->autoidle_reg)  in omap3_dpll_deny_idle()
694 	v = omap2_clk_readl(clk, dd->autoidle_reg);  in omap3_dpll_deny_idle()
695 	v &= ~dd->autoidle_mask;  in omap3_dpll_deny_idle()
696 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);  in omap3_dpll_deny_idle()
697 	omap2_clk_writel(v, clk, dd->autoidle_reg);  in omap3_dpll_deny_idle()
739 	const struct dpll_data *dd;  in omap3_clkoutx2_recalc()  local
752 	dd = pclk->dpll_data;  in omap3_clkoutx2_recalc()
754 	WARN_ON(!dd->enable_mask);  in omap3_clkoutx2_recalc()
756 	v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;  in omap3_clkoutx2_recalc()
757 	v >>= __ffs(dd->enable_mask);  in omap3_clkoutx2_recalc()
758 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))  in omap3_clkoutx2_recalc()
774 	const struct dpll_data *dd;  in omap3_clkoutx2_round_rate()  local
786 	dd = pclk->dpll_data;  in omap3_clkoutx2_round_rate()
789 	if (dd->flags & DPLL_J_TYPE) {  in omap3_clkoutx2_round_rate()
794 	WARN_ON(!dd->enable_mask);  in omap3_clkoutx2_round_rate()
796 	v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;  in omap3_clkoutx2_round_rate()
797 	v >>= __ffs(dd->enable_mask);  in omap3_clkoutx2_round_rate()