Lines Matching refs:ck_dpll1
84 static struct clk ck_dpll1 = { variable
98 .parent = &ck_dpll1,
122 .parent = &ck_dpll1,
133 .parent = &ck_dpll1,
152 .parent = &ck_dpll1,
214 .parent = &ck_dpll1,
226 .parent = &ck_dpll1,
236 .parent = &ck_dpll1,
267 .parent = &ck_dpll1,
387 .parent = &ck_dpll1,
400 .parent = &ck_dpll1,
676 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
760 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, in omap1_show_rates()
837 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ in omap1_clk_init()
841 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; in omap1_clk_init()
842 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; in omap1_clk_init()
849 ck_dpll1.rate /= 2; in omap1_clk_init()
852 ck_dpll1.rate /= 4; in omap1_clk_init()
857 propagate_rate(&ck_dpll1); in omap1_clk_init()
910 unsigned long rate = ck_dpll1.rate; in omap1_clk_late_init()
919 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; in omap1_clk_late_init()
921 propagate_rate(&ck_dpll1); in omap1_clk_late_init()
923 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); in omap1_clk_late_init()