Lines Matching refs:apcr
30 uint32_t awucrm = 0, apcr = 0; in pxa910_set_wake() local
38 apcr |= MPMU_APCR_SLPWP2; in pxa910_set_wake()
43 apcr |= MPMU_APCR_SLPWP3; in pxa910_set_wake()
47 apcr |= MPMU_APCR_SLPWP3; in pxa910_set_wake()
51 apcr |= MPMU_APCR_SLPWP3; in pxa910_set_wake()
56 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
60 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
64 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
68 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
72 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
76 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
80 apcr |= MPMU_APCR_SLPWP4; in pxa910_set_wake()
86 apcr |= MPMU_APCR_SLPWP5; in pxa910_set_wake()
93 apcr |= MPMU_APCR_SLPWP6; in pxa910_set_wake()
98 apcr |= MPMU_APCR_SLPWP7; in pxa910_set_wake()
103 apcr |= MPMU_APCR_SLPWP2; in pxa910_set_wake()
116 if (apcr) { in pxa910_set_wake()
117 apcr = ~apcr & __raw_readl(MPMU_APCR); in pxa910_set_wake()
118 __raw_writel(apcr, MPMU_APCR); in pxa910_set_wake()
125 if (apcr) { in pxa910_set_wake()
126 apcr |= __raw_readl(MPMU_APCR); in pxa910_set_wake()
127 __raw_writel(apcr, MPMU_APCR); in pxa910_set_wake()
135 uint32_t idle_cfg, apcr; in pxa910_pm_enter_lowpower_mode() local
138 apcr = __raw_readl(MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
140 apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD in pxa910_pm_enter_lowpower_mode()
148 apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD; in pxa910_pm_enter_lowpower_mode()
151 apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */ in pxa910_pm_enter_lowpower_mode()
152 apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */ in pxa910_pm_enter_lowpower_mode()
155 apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */ in pxa910_pm_enter_lowpower_mode()
158 apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */ in pxa910_pm_enter_lowpower_mode()
176 apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD in pxa910_pm_enter_lowpower_mode()
180 apcr |= MPMU_APCR_SLPEN; in pxa910_pm_enter_lowpower_mode()
184 __raw_writel(apcr, MPMU_APCR); in pxa910_pm_enter_lowpower_mode()