Lines Matching refs:parent
121 clk = clk->parent; in local_return_parent_rate()
191 .parent = &osc_32KHz,
262 clkin = clk_armpll.parent->rate; in local_update_armpll_rate()
368 .parent = &clk_sys,
383 return clk_check_pll_setup(clk_usbpll.parent->rate, in local_clk_usbpll_setup()
487 clkin = clk->get_rate(clk->parent); in local_usbpll_set_rate()
518 .parent = &osc_main,
534 .parent = &clk_armpll,
539 .parent = &clk_armpll,
561 .parent = &clk_pclk,
568 .parent = &clk_pclk,
575 .parent = &clk_pclk,
582 .parent = &clk_pclk,
589 .parent = &clk_pclk,
596 .parent = &clk_pclk,
603 .parent = &clk_pclk,
610 .parent = &clk_hclk,
618 .parent = &clk_pclk,
631 .parent = &clk_pclk,
639 .parent = &clk_pclk,
647 .parent = &clk_pclk,
655 .parent = &clk_pclk,
663 .parent = &clk_hclk,
671 .parent = &clk_hclk,
679 .parent = &clk_pclk,
687 .parent = &clk_hclk,
695 .parent = &clk_hclk,
703 .parent = &osc_32KHz,
711 .parent = &clk_hclk,
720 .parent = &clk_hclk,
730 .parent = &clk_hclk,
738 .parent = &clk_hclk,
747 .parent = &clk_hclk,
757 .parent = &osc_32KHz,
777 .parent = &clk_usbpll,
812 .parent = &clk_usbpll,
823 .parent = &clk_usbpll,
851 .parent = &osc_32KHz,
875 clk->rate = clk->get_rate(clk->parent) / divider; in adc_onoff_enable()
886 .parent = &clk_pclk,
927 rate = clk->parent->get_rate(clk->parent); in mmc_get_rate()
943 prate = clk->parent->get_rate(clk->parent); in mmc_round_rate()
960 prate = clk->parent->get_rate(clk->parent); in mmc_set_rate()
975 .parent = &clk_armpll,
995 rate = clk->parent->get_rate(clk->parent); in clcd_get_rate()
1017 prate = clk->parent->get_rate(clk->parent); in clcd_set_rate()
1042 prate = clk->parent->get_rate(clk->parent); in clcd_round_rate()
1058 .parent = &clk_hclk,
1078 if (clk->parent) in local_clk_disable()
1079 local_clk_disable(clk->parent); in local_clk_disable()
1088 if (clk->parent) in local_clk_enable()
1089 ret = local_clk_enable(clk->parent); in local_clk_enable()
1098 else if (clk->parent) in local_clk_enable()
1099 local_clk_disable(clk->parent); in local_clk_enable()
1179 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
1191 return clk->parent; in clk_get_parent()
1252 clk_sys.parent = &osc_main; in clk_init()
1254 clk_sys.parent = &osc_pll397; in clk_init()
1256 clk_sys.rate = clk_sys.parent->rate; in clk_init()
1262 clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div(); in clk_init()
1263 clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div(); in clk_init()