Lines Matching refs:NR_IRQS_LEGACY
82 #define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0)
83 #define MX1_INT_CSI (NR_IRQS_LEGACY + 6)
84 #define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7)
85 #define MX1_DSPA_INT (NR_IRQS_LEGACY + 8)
86 #define MX1_COMP_INT (NR_IRQS_LEGACY + 9)
87 #define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10)
88 #define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11)
89 #define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12)
90 #define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13)
91 #define MX1_INT_LCDC (NR_IRQS_LEGACY + 14)
92 #define MX1_SIM_INT (NR_IRQS_LEGACY + 15)
93 #define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16)
94 #define MX1_RTC_INT (NR_IRQS_LEGACY + 17)
95 #define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18)
96 #define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19)
97 #define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20)
98 #define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21)
99 #define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22)
100 #define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23)
101 #define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24)
102 #define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25)
103 #define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26)
104 #define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27)
105 #define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28)
106 #define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29)
107 #define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30)
108 #define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31)
109 #define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32)
110 #define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33)
111 #define MX1_PWM_INT (NR_IRQS_LEGACY + 34)
112 #define MX1_SDHC_INT (NR_IRQS_LEGACY + 35)
113 #define MX1_INT_I2C (NR_IRQS_LEGACY + 39)
114 #define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40)
115 #define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41)
116 #define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42)
117 #define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43)
118 #define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44)
119 #define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45)
120 #define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46)
121 #define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47)
122 #define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48)
123 #define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49)
124 #define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50)
125 #define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51)
126 #define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52)
127 #define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53)
128 #define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55)
129 #define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56)
130 #define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57)
131 #define MX1_TIM2_INT (NR_IRQS_LEGACY + 58)
132 #define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
133 #define MX1_DMA_ERR (NR_IRQS_LEGACY + 60)
134 #define MX1_DMA_INT (NR_IRQS_LEGACY + 61)
135 #define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62)
136 #define MX1_WDT_INT (NR_IRQS_LEGACY + 63)