321 	void __iomem *pll_base;  in mx50_clocks_init()  local
324 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx50_clocks_init()
325 	WARN_ON(!pll_base);  in mx50_clocks_init()
326 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx50_clocks_init()
328 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx50_clocks_init()
329 	WARN_ON(!pll_base);  in mx50_clocks_init()
330 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx50_clocks_init()
332 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx50_clocks_init()
333 	WARN_ON(!pll_base);  in mx50_clocks_init()
334 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx50_clocks_init()
383 	void __iomem *pll_base;  in mx51_clocks_init()  local
386 	pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);  in mx51_clocks_init()
387 	WARN_ON(!pll_base);  in mx51_clocks_init()
388 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx51_clocks_init()
390 	pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);  in mx51_clocks_init()
391 	WARN_ON(!pll_base);  in mx51_clocks_init()
392 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx51_clocks_init()
394 	pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);  in mx51_clocks_init()
395 	WARN_ON(!pll_base);  in mx51_clocks_init()
396 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx51_clocks_init()
472 	void __iomem *pll_base;  in mx53_clocks_init()  local
475 	pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);  in mx53_clocks_init()
476 	WARN_ON(!pll_base);  in mx53_clocks_init()
477 	clk[IMX5_CLK_PLL1_SW]		= imx_clk_pllv2("pll1_sw", "osc", pll_base);  in mx53_clocks_init()
479 	pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);  in mx53_clocks_init()
480 	WARN_ON(!pll_base);  in mx53_clocks_init()
481 	clk[IMX5_CLK_PLL2_SW]		= imx_clk_pllv2("pll2_sw", "osc", pll_base);  in mx53_clocks_init()
483 	pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);  in mx53_clocks_init()
484 	WARN_ON(!pll_base);  in mx53_clocks_init()
485 	clk[IMX5_CLK_PLL3_SW]		= imx_clk_pllv2("pll3_sw", "osc", pll_base);  in mx53_clocks_init()
487 	pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);  in mx53_clocks_init()
488 	WARN_ON(!pll_base);  in mx53_clocks_init()
489 	clk[IMX5_CLK_PLL4_SW]		= imx_clk_pllv2("pll4_sw", "osc", pll_base);  in mx53_clocks_init()