Lines Matching refs:clk_prepare_enable
302 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); in mx5_clocks_common_init()
303 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ in mx5_clocks_common_init()
304 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); in mx5_clocks_common_init()
305 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ in mx5_clocks_common_init()
306 clk_prepare_enable(clk[IMX5_CLK_SPBA]); in mx5_clocks_common_init()
307 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ in mx5_clocks_common_init()
308 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ in mx5_clocks_common_init()
309 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); in mx5_clocks_common_init()
310 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); in mx5_clocks_common_init()
311 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); in mx5_clocks_common_init()
312 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); in mx5_clocks_common_init()
313 clk_prepare_enable(clk[IMX5_CLK_TMAX1]); in mx5_clocks_common_init()
314 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ in mx5_clocks_common_init()
315 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ in mx5_clocks_common_init()
371 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); in mx50_clocks_init()
448 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); in mx51_clocks_init()
566 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); in mx53_clocks_init()