79 static void set_cpu_hi3620(int cpu, bool enable)  in set_cpu_hi3620()  argument
85 		if ((cpu == 2) || (cpu == 3))  in set_cpu_hi3620()
86 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),  in set_cpu_hi3620()
91 		writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);  in set_cpu_hi3620()
96 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);  in set_cpu_hi3620()
99 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);  in set_cpu_hi3620()
102 		if ((cpu == 2) || (cpu == 3))  in set_cpu_hi3620()
103 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),  in set_cpu_hi3620()
109 		val &= ~(CPU0_WFI_MASK_CFG << cpu);  in set_cpu_hi3620()
115 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);  in set_cpu_hi3620()
119 		val |= (CPU0_WFI_MASK_CFG << cpu);  in set_cpu_hi3620()
123 		writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);  in set_cpu_hi3620()
125 		if ((cpu == 2) || (cpu == 3)) {  in set_cpu_hi3620()
127 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),  in set_cpu_hi3620()
135 		writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);  in set_cpu_hi3620()
137 		if ((cpu == 2) || (cpu == 3)) {  in set_cpu_hi3620()
139 			writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),  in set_cpu_hi3620()
160 void hi3xxx_set_cpu(int cpu, bool enable)  in hi3xxx_set_cpu()  argument
168 		set_cpu_hi3620(cpu, enable);  in hi3xxx_set_cpu()
183 void hix5hd2_set_cpu(int cpu, bool enable)  in hix5hd2_set_cpu()  argument
215 void hip01_set_cpu(int cpu, bool enable)  in hip01_set_cpu()  argument
265 void hi3xxx_cpu_die(unsigned int cpu)  in hi3xxx_cpu_die()  argument
268 	hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));  in hi3xxx_cpu_die()
272 	panic("cpu %d unexpectedly exit from shutdown\n", cpu);  in hi3xxx_cpu_die()
275 int hi3xxx_cpu_kill(unsigned int cpu)  in hi3xxx_cpu_kill()  argument
279 	while (hi3xxx_get_cpu_jump(cpu))  in hi3xxx_cpu_kill()
282 	hi3xxx_set_cpu(cpu, false);  in hi3xxx_cpu_kill()
286 void hix5hd2_cpu_die(unsigned int cpu)  in hix5hd2_cpu_die()  argument
289 	hix5hd2_set_cpu(cpu, false);  in hix5hd2_cpu_die()