Lines Matching refs:r6
22 orr r6, r2, #FPEXC_EN
23 VFPFMXR FPEXC, r6
33 bic r6, r2, #FPEXC_EX @ FPEXC_EX disable
34 VFPFMXR FPEXC, r6
36 VFPFSTMIA \vfp_base, r6 @ Save VFP registers
42 VFPFLDMIA \vfp_base, r6 @ Load VFP registers
95 mrs r6, r12_fiq
119 msr r12_fiq, r6
173 msr r12_fiq, r6
255 mrrc p15, 0, r6, r7, c2 @ TTBR 0
269 strd r6, r7, [r2]
281 mrc p15, 0, r6, c5, c0, 0 @ DFSR
296 str r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
307 mrc p15, 0, r6, c10, c3, 0 @ AMAIR0
316 str r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
335 ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
341 mcr p15, 0, r6, c10, c3, 0 @ AMAIR0
351 ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
364 mcr p15, 0, r6, c5, c0, 0 @ DFSR
380 ldrd r6, r7, [r12]
392 mcrr p15, 0, r6, r7, c2 @ TTBR 0
418 ldr r6, [r2, #GICH_EISR0]
426 ARM_BE8(rev r6, r6 )
436 str r6, [r11, #(VGIC_V2_CPU_EISR + 4)]
441 str r6, [r11, #VGIC_V2_CPU_EISR]
456 1: ldr r6, [r2], #4
457 ARM_BE8(rev r6, r6 )
458 str r6, [r3], #4
495 1: ldr r6, [r3], #4
496 ARM_BE8(rev r6, r6 )
497 str r6, [r2], #4